NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 76
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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3.8.1.3
76
RID - Revision Identification Register
This register contains the revision number of the MCH. The Revision ID (RID) is a
traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI
header of every PCI/PCI Express compatible device and function. Previously, a new
value for RID was assigned for Intel chipsets for every . There is a a need to provide an
alternative value for software compatibility when a particular driver or patch unique to
that stepping or an earlier stepping is required, for instance, to prevent Windows
software from flagging differences in RID during device enumeration. The solution is to
implement a mechanism to read one of two possible values from the RID register:
Reading the RID in the Intel 5000P Chipset MCH returns either the SRID or CRID
depending on the state of a register select flip-flop. Following reset, the register select
flip flop is reset and the SRID is returned when the RID is read at offset 08h. The SRID
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
1. Stepping Revision ID (SRID): This is the default power on value for mask/metal
2. Compatible Revision ID (CRID): The CRID functionality gives BIOS the flexibility
15:0
Bit
steppings.
to load OS drivers optimized for a previous revision of the silicon instead of the
current revision of the silicon in order to reduce drivers updates and minimize
changes to the OS image for minor optimizations to the silicon for yield
improvement, or feature enhancement reasons that do not negatively impact the
OS driver functionality.
RWO
Attr
0, 2-3, 8, 9
0
02h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
00h
Intel 5000Z Chipset
4-7
0
02h
Intel 5000P Chipset
16
0, 2
02h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
17
0
02h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
21
0
02h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
020h
Intel 5000P Chipset
Table 3-2
Default
*See
Device Identification Number
Identifies each function of the MCH
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Register Description
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