NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 295
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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System Address Map
4.6
4.7
4.7.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Configuration Space
All chipset registers are represented in the memory address map. In addition, some
registers are also mapped as PCI registers in PCI configuration space.These adhere to
the PCI Local Bus Specification, Revision 2.2 .
The memory mapped configuration space is described in
register maps are in the registers chapters of the Intel 5000P Chipset MCH Component
Specifications.
If a CPU issues a zero length configuration cycle accessing the Intel 5000P Chipset
MCH’s internal configuration space registers or the CB_BAR/AMB Memory mapped area,
then it will be completed on the FSB “in order” with no data.
I/O Address Map
The I/O address map is separate from the memory map and is primarily used to
support legacy code/drivers that use I/O mapped accesses rather than memory
mapped I/O accesses. Except for the special addresses listed in “Special I/O addresses”
on page 246, I/O accesses are decoded by range and sent to the appropriate ESI/PCI
Express port, which will route the I/O access to the appropriate device.
Special I/O Addresses
There are two classes of I/O addresses that are specifically decoded by the Intel 5000P
Chipset MCH:
Historically, the 64 K I/O space actually was 64 K+3 bytes. For the extra 3 bytes,
A#[16] is asserted. The Intel 5000P Chipset decodes only A#[15:3] when the request
encoding indicates an I/O cycle. Therefore accesses with A#[16] asserted are decoded
as if they were accesses to address 0 and are forwarded to the Compatibility Bus.
At power-on, all I/O accesses are mapped to the Compatibility Bus.
3. ISA Aliases: If the PCICMD[y].IOAE and BCTRL[y].ISAEN are set to 1 for a PCI
4. I/O defined by IOBASE/IOLIMIT: If PCICMD[y].IOAE is set for a given PCI Express
5. Otherwise, the I/O Read/Write is sent to ESI (Intel 631xESB/632xESB I/O
• I/O addresses used for VGA controllers.
• I/O addresses used for the PCI Configuration Space Enable (CSE) protocol. The I/O
configuration access. Configuration accesses are routed based on the bus and
device numbers as programmed by software.
Express port y and the I/O address falls within (IOBASE[y], IOLIMIT[y]) and if the
addresses are X100-X3FFh, X500-X7FFh, X900-XBFF, and XD00-XFFFh (X can be
any hex number) will result in the access being sent out to the ESI (Intel 631xESB/
632xESB I/O Controller Hub). This is the top 768 B in each 1 KB block.
port and the I/O address falls in this range: (IOBASE[y] <= address <=
IOLIMIT[y]) for that port, then the access will be routed to the PCI Express port y.
Controller Hub).
addresses 0CF8h and 0CFCh are specifically decoded as part of the CSE protocol.
Section
4.3.4. Individual
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