NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 243
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Register Description
3.9.25.9
3.9.25.10
3.9.25.11
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
FBD[3:2]IBRXMSK: IBIST Receiver Mask
This register determines which lanes are enabled for IBIST operations. These bits also
control the power saving features of each lane. If a particular lane is masked off, the
power to that lane is reduced as much as possible.
FBD[1:0]IBRXMSK: IBIST Receiver Mask
This register determines which lanes are enabled for IBIST operations. These bits also
control the power saving features of each lane. If a particular lane is masked off, the
power to that lane is reduced as much as possible.
FBD[3:2]IBTXSHFT: IBIST Transmit Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
31:14
13:10
31:14
31:14
13:0
13:0
9:0
Bit
Bit
Bit
RWST
RWST
RWST
RWST
Attr
Attr
Attr
RV
RV
RV
21
22
21
28Ch, 18Ch
290h, 190h
290h, 190h
Default
Default
Default
1FFFh
1FFFh
3FFh
0h
0h
0h
0h
Reserved
txmaskhvm: Transmit Mask extra DFT pins for HVM symmetry
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
txmask: Transmit Mask
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
Reserved
rxmask: Receive Mask
Selects which lanes to enable for testing. An Rx lane that is not selected is not
included in Rx channel training does not contribute to the accumulation of
error counts.
Reserved
rxmask: Receive Mask
Selects which lanes to enable for testing. An Rx lane that is not selected is not
included in Rx channel training does not contribute to the accumulation of
error counts.
Description
Description
Description
243
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