NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 85
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Register Description
3.8.2.2
3.8.2.3
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PAM1 - Programmable Attribute Map Register 1
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0C 0000h-0C 7FFFh.
PAM2 - Programmable Attribute Map Register 2
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0C 8000h -0C FFFF h.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:6
5:4
3:2
1:0
7:6
5:4
3:2
Bit
Bit
Attr
Attr
RW
RW
RW
RV
RV
RV
RV
16
0
5Ah
Intel 5000P Chipset, Intel 5000V Chipset
16
0
5Bh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
00
00
00
00
00
00
00
Reserved
ESIENABLE1: 0C4000-0C7FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C4000 to 0C7FFF
Bit5 = Write enable, Bit4 = Read enable.
Encoding
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
LOENABLE1: 0C0000-0C3FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C0000 to 0C3FFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
ESIENABLE2: 0CC000-0CFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0CC000-0CFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
Description
Description
Description
Description
Description
85
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