NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 251
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
- Current page: 251 of 530
- Download datasheet (5Mb)
Register Description
3.9.26
3.9.26.1
3.9.26.2
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Serial Presence Detect Registers
There are two sets of the following registers, one set for each FB-DIMM branch. They
each appear in function 0 of different devices as shown in
SPD[1:0][1:0] - Serial Presence Detect Status Register
This register provides the interface to the SPD bus (SCL and SDA signals) that is used
to access the Serial Presence Detect EEPROM that defines the technology,
configuration, and speed of the DIMM’s controlled by the MCH.
SPDCMD[1:0][1:0] - Serial Presence Detect Command Register
A write to this register initiates a DIMM EEPROM access through the SPD bus.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
11:8
7:0
Bit
15
14
13
12
Attr
RO
RO
RO
RO
RO
RV
21
0
76h, 74h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
76h, 74h
Intel 5000P Chipset
Default
00h
0h
0
0
0
0
RDO: Read Data Valid.
This bit is set by the AMB when the Data field of this register receives read data
from the SPD EEPROM after successful completion of an SPDR command. It is
cleared by the Intel 5000P Chipset MCH when a subsequent SPDR command is
issued.
WOD: Write Operation Done.
This bit is set by the Intel 5000P Chipset MCH when a SPDW command has been
completed on the SPD bus. It is cleared by the Intel 5000P Chipset MCH when a
subsequent SPDW command is issued.
SBE: SPD Bus Error.
This bit is set by the Intel 5000P Chipset MCH if it initiates an SPD bus transaction
that does not complete successfully. It is cleared by the AMB when an SPDR or
SPDW command is issued.
BUSY: Busy state.
This bit is set by the Intel 5000P Chipset MCH while an SPD command is executing.
Reserved.
DATA: Data.
Holds data read from SPDR commands.
Description
Table 3-3.
251
Related parts for NQ5000P S L9TN
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
5000P Memory Controller Hub (MCH)
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Microprocessor: Intel Celeron M Processor 320 and Ultra Low Voltage Intel Celeron M Processor at 600MHz
Manufacturer:
Intel Corporation
Part Number:
Description:
Intel 82550 Fast Ethernet Multifunction PCI/CardBus Controller
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 120 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 120 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 64 Mbit. Access speed 150 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 100 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
DA28F640J5A-1505 Volt Intel StrataFlash Memory
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
5 Volt Intel StrataFlash?? Memory
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
5 Volt Intel StrataFlash?? Memory
Manufacturer:
Intel Corporation
Part Number:
Description:
Intel 6300ESB I/O Controller Hub
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel 82801DB I/O Controller Hub (ICH4), Pb-Free SLI
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel 82801FB I/O Controller Hub (ICH6)
Manufacturer:
Intel Corporation
Datasheet: