NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 375
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Functional Description
Figure 5-1.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
1. Intel 5000P Chipset MCH VPP supports PCA9555 or compatible I/O Extender only.
PCI Express Hot-Plug/VPP Block Diagram
The Intel 5000P Chipset MCH masters a 100KHz hot-plug SMBus interface thru pins
GPIOSMBCLK,and GPIOSMBDATA, for PCI Express ports that connect to a variable
number of serial to parallel I/O ports such as the Phillips PCA9555
Intel 5000P Chipset MCH only supports SMBus devices with registers mapped as per
Table
that can be configured as inputs or outputs. The Intel 5000P Chipset MCH has a
crossbar which associates each PCI Express Hot-Plug Unit (HPU) slots with one of these
8-bit ports. The mapping is defined by a Virtual Pin Port register field, PEXCTRL.VPP, for
each of the PCI Express HPU slots. The VPP register holds the SMBus address and port
number of the IO Port associated with the PCI Express HPU. A[2:0] pins on each I/O
Extender (that is, PCA9555 or compatible components) connected to the Intel 5000P
Chipset MCH must strapped uniquely.
are mapped to pins on the VPP.
5-25. These I/O Extender components have 16 I/Os, divided into two 8-bit ports
ICH6/ESB
Button
LED
Slot 0
A2 A1 A0
I/O extender 0
Button
LED
Slot 1
Intel ® 5000P chipset
INTx
Button
LED
Slot 2
I/O extender 1
Table 5-26
FSB 0
Slot 3
Button
(P2P bridge, HPC)
LED
PEX Root Port
100K Hz SM Bus
VPP
defines how the eight hot-plug signals
MSI
FSB 1
Board Power
Manager
1
Slot 14
I/O Extender. The
A2 A1 A0
Button
LED
I/O extender 7
Slot 15
Button
LED
375
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