LH79520N0M000B1 NXP Semiconductors, LH79520N0M000B1 Datasheet - Page 17

• Manufacturer Part Number: LH79520N0M000B1
• Manufacturer: NXP Semiconductors

Specifications of LH79520N0M000B1

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.62V
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.98V
• Package Type: LQFP
• Screening Level: Industrial
• Pin Count: 176
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

System-on-Chip
Memory Architecture
Controller provide a glueless interface to external
SDRAM, Flash, SRAM, ROM, and burst ROM. Three
remap options for the physical memory are selectable
by software, as shown in Figures 4, 5, and 6. Memory
is exclusively Little Endian.
SDRAM CONTROLLER
between the internal bus and external (off-chip)
SDRAM memory devices (Figure 2).
• Two independently controlled chip selects.
• Transfers data between the controller and SDRAM
• Supports both 32-bit and 16-bit SDRAM.
• Supports 2K, 4K, and 8K row address memory parts,
• Two reset domains allow SDRAM contents to be
STATIC MEMORY CONTROLLER (SMC)
bus and external (off-chip) memory devices.
address space is divided into eight memory banks of
64 MB each. The SMC supports:
• Static Memory-mapped Devices including RAM,
• Asynchronous Operations:
• 8-, 16-, and 32-bit wide external memory data paths
• Independent configuration for up to eight memory
• Programmable Parameters:
an nWAIT input that can be used by an external device
to vary the wait time.
DMA Controller
capable peripherals. The LCD controller uses its own
DMA port, connecting directly to memory for retrieving
display data.
Preliminary data sheet
in quad-word bursts.
i.e. typical 256M, 128M, 64M, and 16M parts, with 8,
16, or 32 DQ bits per device.
preserved over a soft reset.
ROM, Flash, and Burst ROM
banks, each up to 64 MB
An integrated SDRAM Controller and Static Memory
The SDRAM Controller provides the interface
The SDRAM Controller provides the following features:
The SMC provides the interface between the internal
The LH79520 boots from 16-bit memory. The SMC
– Page Mode Reads for non-clocked memory
– Burst Mode Reads for burst mode ROM
– WAIT States (up to 32)
– Bus Turnaround Cycles (1 to 16)
– Initial and Subsequent Burst Read WAIT State for
The Static Memory Controller (SMC) also supports
The DMA Controller provides support for DMA-
Burst ROM Devices.
Rev. 01 — 16 July 2007
NXP Semiconductors
0xFFFFFFFF
0xFFFC0000
0xFFFFFFFF
0xFFFF0000
0xFFFC0000
0xFFFF0000
0x80000000
0x60000000
0x40000000
0x20000000
0x00000000
0xFFFFFFFF
0x80000000
0x60000000
0x40000000
0x20000000
0x00000000
0xFFFC0000
Figure 4. Memory Remap ‘00’ and ‘11’
0xFFFF0000
0x80000000
0x60000000
0x40000000
0x20000000
0x00000000
Figure 5. Memory Remap ‘10’
Figure 6. Memory Remap ‘01’
ADVANCED HIGH-PERFORMANCE BUS
ADVANCED HIGH-PERFORMANCE BUS
ADVANCED HIGH-PERFORMANCE BUS
ADVANCED PERIPHERAL BUS
ADVANCED PERIPHERAL BUS
EXTERNAL STATIC MEMORY
INTERNAL STATIC MEMORY
INTERNAL STATIC MEMORY
ADVANCED PERIPHERAL BUS
EXTERNAL STATIC MEMORY
EXTERNAL STATIC MEMORY
INTERNAL STATIC MEMORY
EXTERNAL STATIC MEMORY
INTERNAL STATIC MEMORY
PERIPHERALS
PERIPHERALS
PERIPHERALS
PERIPHERALS
PERIPHERALS
PERIPHERALS
RESERVED
RESERVED
RESERVED
SDRAM
SDRAM
SDRAM
SDRAM
LH79520
79520-3
79520-5
79520-4
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