PNX1311EH/G NXP Semiconductors, PNX1311EH/G Datasheet - Page 506
PNX1311EH/G
Manufacturer Part Number
PNX1311EH/G
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1311EHG.pdf
(548 pages)
Specifications of PNX1311EH/G
Lead Free Status / RoHS Status
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Philips Semiconductors
Write source program counter
SYNTAX
FUNCTION
DESCRIPTION
hardware update (during an interruptible jump) and a software update (through a
update takes precedence.
writes its target address to SPC. The value of SPC is intended to allow an exception-handling routine to determine the
start address of the block of scheduled code (called a decision tree) that was executing before the exception was
taken.
modification of SPC. If the LSB of rguard is 1, SPC is written; otherwise, SPC is unchanged.
EXAMPLES
r30 = 0xbeebee
r20 = 0, r31 = 0xabba
r21 = 1, r31 = 0xabba
The
An interruptible jump that is not interrupted (no NMI, INT, or EXC event was pending when the jump was executed)
The
[ IF rguard ] writespc rsrc1
if rguard then
SPC ← rsrc1
writespc
writespc
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
copies the value of rsrc1 to the SPC (Source Program Counter) processor register. Whenever a
writespc r30
IF r20 writespc r31
IF r21 writespc r31
Operation
PRELIMINARY SPECIFICATION
SPC ← 0xbeebee
no change, since guard is false
SPC ← 0xabba
PNX1300/01/02/11 DSPCPU Operations
writespc
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
readspc writedpc ijmpf
Result
ijmpi ijmpt
ATTRIBUTES
SEE ALSO
) coincide, the software
writespc
fcomp
159
No
—
1
1
3
A-208
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