PNX1311EH/G NXP Semiconductors, PNX1311EH/G Datasheet - Page 514
PNX1311EH/G
Manufacturer Part Number
PNX1311EH/G
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1311EHG.pdf
(548 pages)
Specifications of PNX1311EH/G
Lead Free Status / RoHS Status
Compliant
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PNX1300/01/02/11 Data Book
B-4
AI_FREQ
AI_BASE1
AI_BASE2
AI_SIZE
AO_STATUS
AO_CTL
AO_SERIAL
AO_FRAMING
AO_FREQ
AO_BASE1
AO_BASE2
AO_SIZE
AO_CC
AO_CFC
AO_TSTAMP
SDO_STATUS
SDO_CTL
SDO_FREQ
SDO_BASE1
SDO_BASE2
SDO_SIZE
SDO_TSTAMP
BIU_STATUS
BIU_CTL
PCI_ADR
PCI_DATA
CONFIG_ADR
CONFIG_DATA
CONFIG_CTL
IO_ADR
IO_DATA
IO_CTL
SRC_ADR
DEST_ADR
DMA_CTL
INT_CTL
XIO_CTL
JTAG_DATA_IN
JTAG_DATA_OUT
JTAG_CTL
MMIO Register Name
PRELIMINARY SPECIFICATION
10 4C0C
10 4C00
10 4C04
10 4C08
10 4C10
10 4C14
10 4C18
(in hex)
10 1c10
10 1c14
10 1c18
10 1c1c
10 2000
10 2004
10 2008
10 200c
10 2010
10 2014
10 2018
10 201c
10 2020
10 2024
10 2028
10 3004
10 3008
10 300c
10 3010
10 3014
10 3018
10 301c
10 3020
10 3024
10 3028
10 302c
10 3030
10 3034
10 3038
10 3060
10 3800
10 3804
10 3808
Offset
DSPCPU
R/—
R/—
R/—
R/—
R/—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Accessibility
Image Co-Processor
Initiators
PCI Interface
External
SPDIF Out
Audio Out
—/—
—/—
R/—
R/—
R/—
R/—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCI
JTAG
Sets AI_OSCLK frequency
Sets base address of buffer 1
Sets base address of buffer 2
Sets number of samples in buffers
Status of audio-out unit
Sets operation and interrupt modes for audio out
Sets clock ratios and internal/external clock generation
Sets format of serial data stream
Set AO_OSCLK frequency
Sets base address of buffer 1
Sets base address of buffer 2
Sets number of samples in buffers
Codec control field values
Codec Frame Control
Timestamp of the last buffer
Status register
Control register
Frequency register
Base address of buffer 1
Base address of buffer 2
Number of samples in buffers
Timestamp of the last buffer
Status of PCI interface (done/busy bits, error bits)
Sets operation and interrupt modes for PCI
Holds address for DSPCPU PCI access
Holds data for DSPCPU PCI access
Holds address for configuration access
Holds data for configuration access
Sets read/write, bus number for configuration access
Holds address for I/O access
Holds data for I/O access
Sets read/write, byte-enable for I/O access
Holds source address for DMA operation
Holds destination address for DMA operation
Sets read/write, transfer length for DMA operation
Controls interrupt system
XIO control register
JTAG data input buffer
JTAG data output buffer
JTAG control
Description
Philips Semiconductors
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