IDT82V3202NLG8 IDT, Integrated Device Technology Inc, IDT82V3202NLG8 Datasheet
IDT82V3202NLG8
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IDT82V3202NLG8 Summary of contents
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EBU WAN PLL IDT82V3202 Version 5 September 11, 2009 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. © 2009 Integrated Device Technology, Inc. ...
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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any ...
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FEATURES .............................................................................................................................................................................. 9 HIGHLIGHTS.................................................................................................................................................................................................... 9 MAIN FEATURES ............................................................................................................................................................................................ 9 OTHER FEATURES ......................................................................................................................................................................................... 9 APPLICATIONS....................................................................................................................................................................... 9 DESCRIPTION....................................................................................................................................................................... 10 FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11 1 PIN ASSIGNMENT ........................................................................................................................................................... 12 2 PIN DESCRIPTION .......................................................................................................................................................... 14 3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 18 3.1 RESET ........................................................................................................................................................................................................... ...
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IDT82V3202 3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 32 3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 32 3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 32 3.10.1.5.4 Manual ........................................................................................................................................................... 32 3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 32 3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 32 3.11 DPLL OUTPUT .............................................................................................................................................................................................. 34 3.11.1 ...
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IDT82V3202 8.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 105 8.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 106 8.7 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 107 PACKAGE DIMENSIONS.................................................................................................................................................... 112 ORDERING INFORMATION................................................................................................................................................ 117 DATASHEET DOCUMENT HISTORY................................................................................................................................. 117 5 EBU WAN PLL September 11, 2009 ...
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Table 1: Pin Description ............................................................................................................................................................................................. 14 Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 18 Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 19 Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 20 Table ...
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IDT82V3202 Table 48: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 104 Table 49: Input/Output Clock Timing ......................................................................................................................................................................... 106 Table 50: Output Clock Timing .................................................................................................................................................................................. 107 7 EBU WAN PLL September 11, 2009 ...
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Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11 Figure 2. Pin Assignment (NL68 Top View) ................................................................................................................................................................ 12 Figure 3. Pin Assignment (TQFP 64 Top View) .......................................................................................................................................................... 13 Figure 4. Pre-Divider for An Input Clock ..................................................................................................................................................................... 20 Figure 5. Input Clock Activity ...
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FEATURES HIGHLIGHTS • The first single PLL chip: - Features 0 560 Hz bandwidth - Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements - Provides node clocks for Cellular and WLL base-station (GSM and ...
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IDT82V3202 DESCRIPTION The IDT82V3202 is an integrated, single-chip solution for the Syn- chronous Equipment Timing Source for Stratum 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, ...
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IDT82V3202 FUNCTIONAL BLOCK DIAGRAM Functional Block Diagram Figure 1. Functional Block Diagram 11 EBU WAN PLL September 11, 2009 ...
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IDT82V3202 1 PIN ASSIGNMENT AGND 1 IC1 2 AGND1 3 VDDA1 INT_REQ 6 OSCI 7 DGND1 8 VDDD1 9 10 VDDD3 DGND3 11 DGND2 12 VDDD2 13 FF_SRCSW 14 VDDA2 15 AGND2 16 IC2 17 Pin Assignment ...
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IDT82V3202 AGND 1 IC1 2 AGND1 3 VDDA1 4 5 INT_REQ 6 OSCI DGND1 7 8 VDDD1 VDDD3 9 DGND3 10 11 DGND2 12 VDDD2 FF_SRCSW 13 VDDA2 14 15 AGND2 IC2 16 Pin Assignment IDT82V3202 (TQFP 64) Figure 3. ...
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IDT82V3202 2 PIN DESCRIPTION Table 1: Pin Description Pin No. Pin No. Name (NL68) (TQFP 64) OSCI 7 6 FF_SRCSW 14 13 SONET/SDH RST EX_SYNC1 30 28 EX_SYNC2 35 33 IN1_CMOS 31 29 IN2_CMOS 32 30 ...
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IDT82V3202 Table 1: Pin Description (Continued) Pin No. Pin No. Name (NL68) (TQFP 64) OUT2 59 56 INT_REQ 6 5 AD0 47 44 AD1 48 45 AD2 49 46 SCL 50 47 SDA TRST TMS 43 ...
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IDT82V3202 Table 1: Pin Description (Continued) Pin No. Pin No. Name (NL68) (TQFP 64) VDDA1 4 4 VDDA2 15 14 VDDA3 60 57 VDD_DIFF 23 22 DGND1 8 7 DGND2 12 11 DGND3 11 10 DGND4 33 31 DGND5 42 ...
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IDT82V3202 Table 1: Pin Description (Continued) Pin No. Pin No. Name (NL68) (TQFP 64) IC1 2 2 IC2 17 16 IC3 24 23 IC4 25 24 IC5 26 25 IC6 27 26 IC7 36 34 IC8 37 35 IC9 44 ...
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IDT82V3202 3 FUNCTIONAL DESCRIPTION 3.1 RESET The reset operation resets all registers and state machines to their default value or status. After power on, the device must be reset for normal operation. For a complete reset, the RST pin must ...
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IDT82V3202 3.3 INPUT CLOCKS & FRAME SYNC SIGNALS Altogether two clocks and two frame sync signals are input to the device. 3.3.1 INPUT CLOCKS The device provides two CMOS input clock ports: IN1_CMOS and IN2_CMOS. According to the input clock ...
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IDT82V3202 3.4 INPUT CLOCK PRE-DIVIDER Each input clock is assigned an internal Pre-Divider. The Pre-Divider is used to divide the clock frequency down to the DPLL required fre- quency, which is no more than 38.88 MHz. For each input clock, ...
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IDT82V3202 3.5 INPUT CLOCK QUALITY MONITORING The qualities of the input clocks are always monitored in the following aspects: • Activity • Frequency The qualified clocks are available for T0 DPLL selection. The T0 selected input clock has to be ...
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IDT82V3202 3.5.2 FREQUENCY MONITORING Frequency is monitored by comparing the input clock with a refer- ence clock. The reference clock can be derived from the master clock or the output of T0 DPLL, as determined by the FREQ_MON_CLK bit. A ...
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IDT82V3202 3.6 DPLL INPUT CLOCK SELECTION The EXT_SW bit and the T0_INPUT_SEL[3:0] bits determine the input clock selection, as shown in Table Table 6: Input Clock Selection Control Bits EXT_SW T0_INPUT_SEL[3:0] 1 don’t-care other than 0000 0 0000 External Fast ...
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IDT82V3202 3.6.2 FORCED SELECTION In Forced selection, the selected input clock is set by the T0_INPUT_SEL[3:0] bits. The results of input clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality input clock selection. 3.6.3 AUTOMATIC SELECTION In Automatic selection, ...
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IDT82V3202 3.7 SELECTED INPUT CLOCK MONITORING The quality of the selected input clock is always monitored (refer to Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status is always monitored. 3.7.1 DPLL LOCKING DETECTION The following events is ...
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IDT82V3202 The phase lock alarm can be cleared by the following two ways, as selected by the PH_ALARM_TIMEOUT bit: • Be cleared when a ‘1’ is written to the corresponding INn_CMOS_PH_LOCK_ALARM bit; • Be cleared after the period (= TIME_OUT_VALUE[5:0] ...
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IDT82V3202 3.8 SELECTED INPUT CLOCK SWITCH If the input clock is selected by External Fast selection or by Forced selection, it can be switched by setting the related registers (refer to Chapter 3.6.1 External Fast Selection & any time. In ...
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IDT82V3202 Table 13: Related Bit / Register in Chapter 3.8 Bit 1 INn_CMOS ( INn_CMOS ( INn_CMOS ( INn_CMOS_NO_ACTIVITY_ALARM ( INn_CMOS_FREQ_HARD_ALARM (n ...
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IDT82V3202 3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE T0 DPLL supports three primary operating modes: Free-Run, Locked and Holdover, and three secondary, temporary operating modes: Pre- Locked, Pre-Locked2 and Lost-Phase. The operating mode of T0 DPLL can be ...
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IDT82V3202 Notes to Figure 7: 1. Reset input clock is selected. 3. The T0 selected input clock is disqualified AND No qualified input clock is available. 4. The T0 selected input clock is switched to another one. 5. ...
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IDT82V3202 3.10 DPLL OPERATING MODE The T0 DPLL gives a stable performance in different applications without being affected by operating conditions or silicon process varia- tions. It integrates a PFD (Phase & Frequency Detector), a LPF (Low Pass Filter) and ...
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IDT82V3202 phase locked to any input clock. The frequency offset acquiring method is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the FAST_AVG bit, as shown in Table 17: Table 17: Frequency Offset Control in Holdover Mode MAN_HOLDOVER AUTO_AVG ...
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IDT82V3202 Table 19: Related Bit / Register in Chapter 3.10 Bit CURRENT_PH_DATA[15:0] CURRENT_DPLL_FREQ[23:0] T0_DPLL_START_BW[4:0] T0_DPLL_START_DAMPING[2:0] T0_DPLL_ACQ_BW[4:0] T0_DPLL_ACQ_DAMPING[2:0] T0_DPLL_LOCKED_BW[4:0] T0_DPLL_LOCKED_DAMPING[2:0] AUTO_BW_SEL FAST_LOS_SW TEMP_HOLDOVER_MODE[1:0] MAN_HOLDOVER AUTO_AVG FAST_AVG READ_AVG T0_HOLDOVER_FREQ[23:0] Functional Description Register CURRENT_DPLL_PHASE[15:8]_STS, CURRENT_DPLL_PHASE[7:0]_STS CURRENT_DPLL_FREQ[23:16]_STS, CURRENT_DPLL_FREQ[15:8]_STS, CURRENT_DPLL_FREQ[7:0]_STS T0_DPLL_START_BW_DAMPING_CNFG T0_DPLL_ACQ_BW_DAMPING_CNFG T0_DPLL_LOCKED_BW_DAMPING_CNFG T0_BW_OVERSHOOT_CNFG PHASE_LOSS_FINE_LIMIT_CNFG ...
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IDT82V3202 3.11 DPLL OUTPUT The DPLL output is locked to the selected input clock. According to the phase-compared result of the feedback and the selected input clock, and the DPLL output frequency offset, the PFD output is limited and the ...
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IDT82V3202 Table 20: Related Bit / Register in Chapter 3.11 Bit MULTI_PH_APP T0_LIMT PBO_EN PBO_FREZ PH_MON_PBO_EN PH_MON_EN PH_TR_MON_LIMT[3:0] PH_OFFSET_EN IN_SONET_SDH T0_GSM_OBSAI_16E1_16T1_SEL[1:0] T0_12E1_24T1_E3_T3_SEL[1:0] Functional Description Register PHASE_LOSS_COARSE_LIMIT_CNFG T0_BW_OVERSHOOT_CNFG MON_SW_PBO_CNFG PHASE_MON_PBO_CNFG PHASE_OFFSET[9:8]_CNFG INPUT_MODE_CNFG T0_DPLL_APLL_PATH_CNFG 35 EBU WAN PLL Address (Hex ...
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IDT82V3202 3. APLL A T0 APLL and a T4 APLL are provided for a better jitter and wander performance of the device output clocks. The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0] / T4_APLL_BW[1:0] ...
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IDT82V3202 Table 23: Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL OUTn_DIVIDER[3:0] 1 (Output Divider) 77.76 MHz X 4 12E1 X 4 0000 3 0001 622.08 MHz 3 0010 48E1 311.04 MHz 0011 155.52 MHz 24E1 0100 77.76 ...
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IDT82V3202 3.13.2 FRAME SYNC OUTPUT SIGNAL An 8 kHz frame sync signal is output on the FRSYNC_8K pin if enabled by the 8K_EN bit CMOS output. The frame sync signal is derived from the T0 APLL output ...
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IDT82V3202 T0 selected input clock Selected frame sync input signal Frame sync output signals Output clocks Figure 10. 0.5 UI Late Frame Sync Input Signal Timing Table 26: Related Bit / Register in Chapter 3.13 Bit OUT1_PECL_LVDS OUTn_PATH_SEL[3: ...
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IDT82V3202 3.14 INTERRUPT SUMMARY The interrupt sources of the device are as follows: • T0 Input clocks validity change • T0 selected input clock fail • T0 DPLL operating mode switch • External sync alarm All of the above interrupt ...
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IDT82V3202 3.16 LINE CARD APPLICATION Master Clock Board Slave Clock Board Functional Description Clock OC-n Clock Sync IDT82V3202 Sync Clock Sync OC-n Line Card Board Backplane Figure 12. Line Card Application 41 SDH/SONET System Optical signal Chip 155 M, 622 ...
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IDT82V3202 PROGRAMMING INTERFACE 2 The I C bus interface provides access to read and write the registers in the IDT82V3202. SDA MSB SCL START or repeated START condition I2C Programming Interface 4.1 ...
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IDT82V3202 4.1.1 DATA TRANSFER FORMAT Two kinds of data transfer formats are supported by the IDT82V3202: • Slave-receiver mode (Write); • Slave-transmitter mode (Read); 4.1.1.1 Slave-receiver Mode (Write) The Slave-receiver mode is as shown in The Master device asserts the ...
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IDT82V3202 4.1.2 ADDRESS ASSIGNMENT AD2 1 1 Figure 16. Address Assignment 4.2 TIMING DEFINITION 2 The timing of I C-bus is as shown in SDA LOW r SCL t ...
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IDT82V3202 Table 29: Timing Definition for Standard Mode and Fast Mode Symbol Parameter SCL Serial clock frequency Hold time (repeated) START condition. After this period, the t HD; STA first clock pulse is generated t LOW period of the SCL ...
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IDT82V3202 5 JTAG This device is compliant with the IEEE 1149.1 Boundary Scan stan- dard except the following: • The output boundary scan cells do not capture data from the core and the device does not support EXTEST instruction; • ...
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IDT82V3202 6 PROGRAMMING INFORMATION After reset, all the registers are set to their default values. The regis- ters are read or written via the microprocessor interface. Before any write operation, PROTECTION_CNFG is recommended to be confirmed to make sure whether ...
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IDT82V3202 Table 31: Register List and Map (Continued) Address Register Name (Hex) INTERRUPTS1_STS - Interrupt Status 0D 1 INTERRUPTS2_STS - Interrupt Status 0E 2 INTERRUPTS3_STS - Interrupt Status 0F 3 INTERRUPTS1_ENABLE_CNFG 10 Interrupt Control 1 INTERRUPTS2_ENABLE_CNFG 11 Interrupt Control 2 ...
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IDT82V3202 Table 31: Register List and Map (Continued) Address Register Name (Hex) BUCKET_SIZE_1_CNFG - Bucket 37 Size for Leaky Bucket Configuration 1 DECAY_RATE_1_CNFG - Decay Rate 38 for Leaky Bucket Configuration 1 UPPER_THRESHOLD_2_CNFG 39 Upper Threshold for Leaky Bucket Configuration ...
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IDT82V3202 Table 31: Register List and Map (Continued) Address Register Name (Hex) T0_DPLL_APLL_PATH_CNFG - T0 55 DPLL & APLL Path Configuration T0_DPLL_START_BW_DAMPING_C 56 NFG - T0 DPLL Start Bandwidth & Damping Factor Configuration T0_DPLL_ACQ_BW_DAMPING_CNF DPLL Acquisition ...
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IDT82V3202 Table 31: Register List and Map (Continued) Address Register Name (Hex) T0_T4_APLL_BW_CNFG - APLL Bandwidth Configuration OUT2_FREQ_CNFG - Output Clock 2 6D Frequency Configuration OUT1_FREQ_CNFG - Output Clock 1 71 Frequency Configuration OUT1_INV_CNFG - Output ...
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IDT82V3202 ID[15:8] - Device ID 2 Address: 01H Type: Read Default Value: 00010001 7 6 ID15 ID14 Bit Name ID[15:8] The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3202. NOMINAL_FREQ[7:0]_CNFG - ...
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IDT82V3202 NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3 Address: 06H Type: Read / Write Default Value: 00000000 7 6 NOMINAL_FRE NOMINAL_FRE Q_VALUE23 Q_VALUE22 Bit Name The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is ...
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IDT82V3202 INPUT_MODE_CNFG - Input Mode Configuration Address: 09H Type: Read / Write Default Value: 10100X10 7 6 AUTO_EXT_SY EXT_SYNC_EN NC_EN Bit Name This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’. 7 AUTO_EXT_SYNC_EN Refer to the ...
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IDT82V3202 DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration Address: 0AH Type: Read / Write Default Value: XXXXX00X Bit Name Reserved. This bit selects a better active edge of ...
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IDT82V3202 MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control Address: 0BH Type: Read / Write Default Value: 100X01X1 7 6 FREQ_MON_C LOS_FLAG_TO ULTR_FAST_SW LK _TDO Bit Name The bit selects a reference clock for input clock frequency monitoring. ...
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IDT82V3202 PROTECTION_CNFG - Register Protection Mode Configuration Address: 7EH Type: Read / Write Default Value: 10000101 7 6 PROTECTION_ PROTECTION_ PROTECTION_ DATA7 DATA6 Bit Name PROTECTION_DATA[7:0] Programming Information 5 4 PROTECTION_ PROTECTION_ DATA5 DATA4 These bits select ...
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IDT82V3202 6.2.2 INTERRUPT REGISTERS INTERRUPT_CNFG - Interrupt Configuration Address: 0CH Type: Read / Write Default Value: XXXXXX10 Bit Name Reserved. This bit determines the output characteristics of the INT_REQ pin. 0: The ...
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IDT82V3202 INTERRUPTS2_STS - Interrupt Status 2 Address: 0EH Type: Read / Write Default Value: 00XXXXXX 7 6 T0_OPERATING T0_MAIN_REF_F _MODE AILED Bit Name 7 T0_OPERATING_MODE 6 T0_MAIN_REF_FAILED INTERRUPTS3_STS - Interrupt Status 3 Address: 0FH Type: Read ...
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IDT82V3202 INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1 Address: 10H Type: Read / Write Default Value: XXXX00XX Bit Name Reserved. This bit controls whether the interrupt is enabled to be reported on the INT_REQ ...
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IDT82V3202 INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3 Address: 12H Type: Read / Write Default Value: 0XXXXXXX 7 6 EX_SYNC_ALARM - Bit Name This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync ...
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IDT82V3202 6.2.3 INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS IN1_CMOS_CNFG - CMOS Input Clock 1 Configuration Address: 16H Type: Read / Write Default Value: 00000000 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the ...
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IDT82V3202 IN2_CMOS_CNFG - CMOS Input Clock 2 Configuration Address: 17H Type: Read / Write Default Value: 00000000 7 6 DIRECT_DIV LOCK_8K Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 17H). This bit, together with the ...
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IDT82V3202 PRE_DIV_CH_CNFG - DivN Divider Channel Selection Address: 23H Type: Read / Write Default Value: XXXX0000 Bit Name PRE_DIV_CH_VALUE[3:0] PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1 ...
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IDT82V3202 PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2 Address: 25H Type: Read / Write Default Value: X0000000 7 6 PRE_DIVN_VAL PRE_DIVN_VAL - UE14 Bit Name PRE_DIVN_VALUE[14:8] Programming Information 5 4 PRE_DIVN_VAL PRE_DIVN_VAL UE13 UE12 ...
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IDT82V3202 IN1_IN2_CMOS_SEL_PRIORITY_CNFG - CMOS Input Clock 1 & 2 Priority Configuration Address: 27H Type: Read / Write Default Value: 00110010 7 6 IN2_CMOS_SE IN2_CMOS_SE IN2_CMOS_SE L_PRIORITY3 L_PRIORITY2 L_PRIORITY1 Bit Name IN2_CMOS_SEL_PRIORITY[3: IN1_CMOS_SEL_PRIORITY[3:0] Programming Information ...
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IDT82V3202 6.2.4 INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration Address: 2EH Type: Read / Write Default Value: XXXX1011 Bit Name FREQ_MON_FACTOR[3:0] ...
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IDT82V3202 UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0 Address: 31H Type: Read / Write Default Value: 00000110 7 6 UPPER_THRE UPPER_THRE SHOLD_0_DAT SHOLD_0_DAT A7 A6 Bit Name UPPER_THRESHOLD_0_DATA[7:0] LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket ...
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IDT82V3202 DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0 Address: 34H Type: Read / Write Default Value: XXXXXX01 Bit Name DECAY_RATE_0_DATA[1:0] UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket ...
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IDT82V3202 BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1 Address: 37H Type: Read / Write Default Value: 00001000 7 6 BUCKET_SIZE BUCKET_SIZE BUCKET_SIZE _1_DATA7 _1_DATA6 Bit Name BUCKET_SIZE_1_DATA[7:0] DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration ...
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IDT82V3202 LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2 Address: 3AH Type: Read / Write Default Value: 00000100 7 6 LOWER_THRE LOWER_THRE LOWER_THRE SHOLD_2_DAT SHOLD_2_DAT SHOLD_2_DAT A7 A6 Bit Name LOWER_THRESHOLD_2_DATA[7:0] BUCKET_SIZE_2_CNFG - Bucket Size for ...
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IDT82V3202 UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3 Address: 3DH Type: Read / Write Default Value: 00000110 7 6 UPPER_THRE UPPER_THRE UPPER_THRE SHOLD_3_DAT SHOLD_3_DAT SHOLD_3_DAT A7 A6 Bit Name UPPER_THRESHOLD_3_DATA[7:0] LOWER_THRESHOLD_3_CNFG - Lower Threshold for ...
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IDT82V3202 DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3 Address: 40H Type: Read / Write Default Value: XXXXXX01 Bit Name DECAY_RATE_3_DATA[1:0] IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel ...
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IDT82V3202 IN1_IN2_CMOS_STS - CMOS Input Clock 1 & 2 Status Address: 44H Type: Read Default Value: X110X110 7 6 IN2_CMOS_FRE IN2_CMOS_NO_ - Q_HARD_ALAR ACTIVITY_ALAR M Bit Name IN2_CMOS_FREQ_HARD_ALARM 5 IN2_CMOS_NO_ACTIVITY_ALARM 4 IN2_CMOS_PH_LOCK_ALARM IN1_CMOS_FREQ_HARD_ALARM 1 ...
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IDT82V3202 6.2.5 T0 DPLL INPUT CLOCK SELECTION REGISTERS INPUT_VALID1_STS - Input Clocks Validity 1 Address: 4AH Type: Read Default Value: XXXX00XX Bit Name Reserved. This bit indicates the validity of the corresponding ...
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IDT82V3202 PRIORITY_TABLE2_STS - Priority Status 2 Address: 4FH Type: Read Default Value: XXXX0000 Bit Name SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration Address: 50H Type: Read / Write ...
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IDT82V3202 6.2.6 T0 DPLL STATE MACHINE CONTROL REGISTERS OPERATING_STS - DPLL Operating Status Address: 52H Type: Read Default Value: 1X0X0001 7 6 EX_SYNC_ALA T0_DPLL_SOFT - RM_MON _FREQ_ALARM Bit Name 7 EX_SYNC_ALARM_MON T0_DPLL_SOFT_FREQ_ALARM T0_DPLL_LOCK 2 ...
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IDT82V3202 T0_OPERATING_MODE_CNFG - T0 DPLL Operating Mode Configuration Address: 53H Type: Read / Write Default Value: XXXXX000 Bit Name T0_OPERATING_MODE[2:0] Programming Information ...
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IDT82V3202 6.2.7 T0 DPLL & T0/T4 APLL CONFIGURATION REGISTERS T0_DPLL_APLL_PATH_CNFG - T0 DPLL & APLL Path Configuration Address: 55H Type: Read / Write Default Value: 00000X0X 7 6 T0_APLL_PATH T0_APLL_PA T0_APLL_PA 3 TH2 Bit Name T0_APLL_PATH[3:0] 3 ...
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IDT82V3202 T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Bandwidth & Damping Factor Configuration Address: 56H Type: Read / Write Default Value: 01101111 7 6 T0_DPLL_STA T0_DPLL_STA T0_DPLL_STA RT_DAMPING2 RT_DAMPING1 RT_DAMPING0 Bit Name T0_DPLL_START_DAMPING[2: T0_DPLL_START_BW[4:0] Programming Information ...
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IDT82V3202 T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration Address: 57H Type: Read / Write Default Value: 01101111 7 6 T0_DPLL_ACQ T0_DPLL_ACQ T0_DPLL_ACQ _DAMPING2 _DAMPING1 Bit Name T0_DPLL_ACQ_DAMPING[2: T0_DPLL_ACQ_BW[4:0] Programming Information 5 ...
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IDT82V3202 T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration Address: 58H Type: Read / Write Default Value: 01101111 7 6 T0_DPLL_LOCK T0_DPLL_LOCK T0_DPLL_LOCK ED_DAMPING2 ED_DAMPING1 Bit Name T0_DPLL_LOCKED_DAMPING[2: T0_DPLL_LOCKED_BW[4:0] T0_BW_OVERSHOOT_CNFG - T0 ...
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IDT82V3202 PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration Address: 5AH Type: Read / Write Default Value: 10000101 7 6 COARSE_PH_L WIDE_EN MULTI_PH_APP OS_LIMT_EN Bit Name This bit controls whether the occurrence of the coarse phase loss will result in ...
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IDT82V3202 PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration Address: 5BH Type: Read / Write Default Value: 10XXX010 7 6 FINE_PH_LOS_ FAST_LOS_SW LIMT_EN Bit Name 7 FINE_PH_LOS_LIMT_EN 6 FAST_LOS_SW PH_LOS_FINE_LIMT[2:0] Programming Information 5 ...
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IDT82V3202 T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration Address: 5CH Type: Read / Write Default Value: 010001XX 7 6 MAN_HOLDOV AUTO_AVG ER Bit Name 7 MAN_HOLDOVER 6 AUTO_AVG 5 FAST_AVG 4 READ_AVG TEMP_HOLDOVER_MODE[1: ...
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IDT82V3202 T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2 Address: 5EH Type: Read / Write Default Value: 00000000 7 6 T0_HOLDOVER T0_HOLDOVER T0_HOLDOVER _FREQ15 _FREQ14 Bit Name T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, ...
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IDT82V3202 CURRENT_DPLL_FREQ[7:0]_STS - DPLL Current Frequency Status 1 Address: 62H Type: Read Default Value: 00000000 7 6 CURRENT_DP CURRENT_DP CURRENT_DP LL_FREQ7 LL_FREQ6 Bit Name CURRENT_DPLL_FREQ[7:0] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H). CURRENT_DPLL_FREQ[15:8]_STS - ...
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IDT82V3202 DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration Address: 65H Type: Read / Write Default Value: 10001100 7 6 FREQ_LIMT_P DPLL_FREQ_S H_LOS OFT_LIMT6 Bit Name 7 FREQ_LIMT_PH_LOS DPLL_FREQ_SOFT_LIMT[6:0] DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL Hard Limit Configuration 1 Address: 66H Type: ...
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IDT82V3202 CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 Address: 68H Type: Read Default Value: 00000000 7 6 CURRENT_PH CURRENT_PH CURRENT_PH _DATA7 _DATA6 Bit Name CURRENT_PH_DATA[7:0] Refer to the description of the CURRENT_PH_DATA[15:8] bits (b7~0, 69H). CURRENT_DPLL_PHASE[15:8]_STS - ...
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IDT82V3202 6.2.8 OUTPUT CONFIGURATION REGISTERS OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration Address: 6DH Type: Read / Write Default Value: 00001000 7 6 OUT2_PATH_S OUT2_PATH_S OUT2_PATH_S EL3 EL2 Bit Name These bits select an input to OUT2. 0000 ~ 0011: ...
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IDT82V3202 OUT1_INV_CNFG - Output Clock 1 Invert Configuration Address:72H Type: Read / Write Default Value: XXXXXX0X Bit Name Reserved. This bit determines whether the output on OUT1 is inverted. 1 OUT1_INV 0: ...
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IDT82V3202 FR_SYNC_CNFG - Frame Sync Output Configuration Address:74H Type: Read / Write Default Value: 01X000XX 7 6 IN_2K_4K_8K_I 8K_EN NV Bit Name 7 IN_2K_4K_8K_INV 6 8K_EN 8K_PUL_POSITION 3 8K_INV 2 8K_PUL Programming Information ...
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IDT82V3202 6.2.9 PBO & PHASE OFFSET CONTROL REGISTERS PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration Address:78H Type: Read / Write Default Value: 0X000110 7 6 IN_NOISE_WIN - DOW Bit Name 7 IN_NOISE_WINDOW PH_MON_EN 4 PH_MON_PBO_EN 3 ...
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IDT82V3202 6.2.10 SYNCHRONIZATION CONFIGURATION REGISTERS SYNC_MONITOR_CNFG - Sync Monitor Configuration Address:7CH Type: Read / Write Default Value: 00101011 7 6 SYNC_BYPASS SYNC_MON_LIMT2 Bit Name This bit selects one frame sync input signal to synchronize the frame sync output signal. 0: ...
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IDT82V3202 7 THERMAL MANAGEMENT The device operates over the industry temperature range -40°C ~ +85°C. To ensure the functionality and reliability of the device, the maxi- mum junction temperature T should not exceed 125°C. In some jmax applications, the device ...
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IDT82V3202 7.4 VFQFPN EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the ...
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IDT82V3202 8 ELECTRICAL SPECIFICATIONS 8.1 ABSOLUTE MAXIMUM RATING Table 34: Absolute Maximum Rating Symbol OUT T STOR 8.2 RECOMMENDED OPERATION CONDITIONS Table 35: Recommended Operation Conditions Symbol Parameter V Power Supply (DC voltage) VDD DD ...
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IDT82V3202 8.3 I/O SPECIFICATIONS 8.3.1 CMOS INPUT / OUTPUT PORT Table 36: CMOS Input Port Electrical Characteristics Parameter Description V Input Voltage High IH V Input Voltage Low IL I Input Current IN V Input Voltage IN Table 37: CMOS ...
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IDT82V3202 Table 39: CMOS Output Port Electrical Characteristics Application Pin Parameter Output Clock Other Output Electrical Specifications Description Min Output Voltage High 2.4 Output ...
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IDT82V3202 8.3.2 PECL / LVDS OUTPUT PORT 8.3.2.1 PECL Output Port Ω (transmission line) OUT1_POS OUT1_NEG 50 Ω (transmission line 3 Figure 20. Recommended PECL Output Port Line Ter- mination ...
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IDT82V3202 8.3.2.2 LVDS Output Port 50 Ω (transmission line) OUT1_POS OUT1_NEG 50 Ω (transmission line) Figure 21. Recommended LVDS Output Port Line Ter- mination Table 41: LVDS Output Port Electrical Characteristics Parameter Description V Input Common-mode Voltage Range CM V ...
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IDT82V3202 8.4 JITTER & WANDER PERFORMANCE Table 42: Output Clock Jitter Generation 1 Test Definition N x 2.048MHz without APLL N x 2.048MHz with T0/T4 APLL N x 1.544 MHz without APLL N x 1.544 MHz with T0/T4 APLL 44.736 ...
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IDT82V3202 Table 43: Output Clock Phase Noise 1 Output Clock 622.08 MHz (T0 DPLL + T0/T4 APLL) 155.52 MHz (T0 DPLL + T0/T4 APLL) 38.88 MHz (T0 DPLL + T0/T4 APLL) 16E1 (T0/T4 APLL) 16T1 (T0/T4 APLL) E3 (T0/T4 APLL) ...
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IDT82V3202 Table 47: Input Jitter Tolerance (8 kHz) Jitter Frequency Jitter Tolerance Amplitude (UI p- 300 Hz 400 Hz 700 Hz 2400 Hz 3600 Hz Table 48: T0 DPLL Jitter Transfer & Damping Factor ...
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IDT82V3202 8.5 OUTPUT WANDER GENERATION template tested result Electrical Specifications Figure 22. Output Wander Generation 105 EBU WAN PLL template tested result September 11, 2009 ...
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IDT82V3202 8.6 INPUT / OUTPUT CLOCK TIMING The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs. 8 kHz Input Clock 8 kHz Output Clock 6.48 MHz Input Clock ...
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IDT82V3202 8.7 OUTPUT CLOCK TIMING Table 50: Output Clock Timing Symbol Electrical Specifications FRSYNC_8K ...
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ADSL --- AMI --- APLL --- ATM --- BITS --- CMOS --- DCO --- DPLL --- DSL --- DSLAM --- DWDM --- EPROM --- GPS --- GSM --- IIR --- IP --- ISDN --- JTAG --- LOS --- ...
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IDT82V3202 PBO --- PDH --- PECL --- PFD --- PLL --- RMS --- PRS --- SDH --- SEC --- SMC --- SONET --- SSU --- STM --- TCM-ISDN --- TDEV --- --- UI WLL --- Glossary Phase Build-Out Plesiochronous Digital ...
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A Averaged Phase Error ........................................................................ 31 B Bandwidths and Damping Factors ..................................................... 31 Acquisition Bandwidth and Damping Factor ............................... 31 Locked Bandwidth and Damping Factor ..................................... 31 Starting Bandwidth and Damping Factor .................................... 31 C Calibration .......................................................................................... 18 Coarse Phase ...
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IDT82V3202 S Selected Input Clock Switch ............................................................... 27 Non-Revertive switch .................................................................. 27 Revertive switch ......................................................................... 27 Index State Machine .................................................................................... 29 V Validity ............................................................................................... 27 111 EBU WAN PLL September 11, 2009 ...
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IDT82V3202 PACKAGE DIMENSIONS Figure 24. 68-Pin NL Package Dimensions (a) (in Millimeters) Package Dimensions 112 EBU WAN PLL September 11, 2009 ...
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IDT82V3202 Figure 25. 68-Pin NL Package Dimensions (b) (in Millimeters) Package Dimensions 113 EBU WAN PLL September 11, 2009 ...
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IDT82V3202 Figure 26. 64-Pin EDG Package Dimensions (a) (in Millimeters) Package Dimensions 114 EBU WAN PLL September 11, 2009 ...
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IDT82V3202 Figure 27. 64-Pin EDG Package Dimensions (b) (in Millimeters) Package Dimensions 115 EBU WAN PLL September 11, 2009 ...
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IDT82V3202 Figure 28. EDG64 Recommended Land Pattern with Exposed Pad (in Millimeters) Package Dimensions 116 EBU WAN PLL September 11, 2009 ...
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IDT82V3202 ORDERING INFORMATION XXXXXXX XX Device Type DATASHEET DOCUMENT HISTORY 3/11/2008 Pages 7, 11, 14, 110, 103, 111, 112, 113, 9/17/2008 Page 108 3/20/2009 Pages 94, 95, 101, 113, 114, 115, 116 7/23/2009 Pages 14, 15, 98 9/11/2009 Page 45 ...