IDT82V3202NLG8 IDT, Integrated Device Technology Inc, IDT82V3202NLG8 Datasheet - Page 43

• Manufacturer Part Number: IDT82V3202NLG8
• Description: IC PLL WAN EBU SGL 68-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3202NLG8

• Input: CMOS
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN, 68-VFQFPN
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3202NLG8

4.1.1
IDT82V3202:
4.1.1.1
bit. The Slave device acknowledges and the Master device delivers the
address byte. The Slave device again acknowledges before the Master
device sends the data byte. The Slave device acknowledges each byte,
and the entire transaction is finished with a STOP condition.
4.1.1.2
device. Then it must follow that address byte with a repeated START
condition to denote a read from that device’s address. The Slave device
then returns one byte data corresponding the address. Note that there is
no STOP condition before the repeated STRAT condition, and that a no-
acknowledge (NACK) signifies the end of the read transfer.
I2C Programming Interface
IDT82V3202
Two kinds of data transfer formats are supported by the
The Slave-receiver mode is as shown in
The Master device asserts the slave address followed by the Write
The Slave-transmitter mode is as shown in
First the Master device must write an address byte to the slave
• Slave-receiver mode (Write);
• Slave-transmitter mode (Read);
S
1
DATA TRANSFER FORMAT
Slave-receiver Mode (Write)
Slave-transmitter Mode (Read)
Slave Address
S
Rd
A
7
S
1
Start Condition
Read (bit value of 1)
Master-to-Slave
Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK)
S
Wr
P
A
Slave Address
Wr
1
Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK)
Start Condition
Write (bit value of 0)
Stop Condition
7
1
A
Figure
Figure
Address Byte
14.
Wr
Figure 15. Slave-transmitter Mode
1
15.
Figure 14. Slave-receiver Mode
8
A
1
Address Byte
A
1
P
Wr
43
8
1
S
Slave Address
Stop Condition
Write (bit value of 0)
Slave-to-Master
A
1
7
Master-to-Slave
Slave-to-Master
Data Byte
Rd
1
8
A
1
A
1
Data Byte
8
1
P
September 11, 2009
EBU WAN PLL
1
A
P
1