IDT82V3202NLG8 IDT, Integrated Device Technology Inc, IDT82V3202NLG8 Datasheet - Page 45

• Manufacturer Part Number: IDT82V3202NLG8
• Description: IC PLL WAN EBU SGL 68-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3202NLG8

• Input: CMOS
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN, 68-VFQFPN
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3202NLG8

Table 29: Timing Definition for Standard Mode and Fast Mode
I2C Programming Interface
IDT82V3202
Note:
1. All values referred to
2. A device must Internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
ing edge of SCL.
3. The maximum t
4. A Fast-mode I
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t
5. C
n/a = not applicable
Symbol
t
t
t
t
t
SU; STO
HD; STA
SU; STA
HD; DAT
SU; DAT
b
t
t
SCL
t
HIGH
V
LOW
V
BUF
= total capacitance of one bus line in pF. If mixed with Hs-mode device, faster fall-times according to
C
t
t
sp
t
nH
nL
r
f
b
Serial clock frequency
Hold time (repeated) START condition. After this period, the
first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time: for CBUS compatible masters for I
devices
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Noise margin at the LOW level for each connected device
(Including hysteresis)
Noise margin at the HIGH level for each connected device
(Including hysteresis)
Pulse width of spikes which must be suppressed by the input
filter
2
C-bus device can be used in a Standard-mode I
HD; DAT
rmax
V
IHmin
+ t
has only to be met if the device does not strech the LOW period (t
SU; DAT
and
V
ILmax
= 1000 + 250 = 1250 ns (according to the Standard-mode I
levels (see
Parameter
Table
37)
2
C-bus system, but the requirement t
2
C-bus
(1)
45
0.1VDD
0.2VDD
Min
250
0
4.0
4.7
4.0
4.7
5.0
4.0
4.7
0
0
(2)
-
-
-
Standard Mode
LOW
2
C-bus specification) before the SCL line is released.
) of the SCL signal.
IHmin
SU; DAT
3.45
1000
Max
100
300
400
50
-
-
-
-
-
-
-
-
-
-
of the SCL signal) to bridge the undefined region of the fall-
Table 39
(3)
≥ 250 ns must then be met. This will automatically be
allowed.
20 + 0.1Cb
20 + 0.1Cb
0.1VDD
0.2VDD
100
Min
0
0.5
1.3
0.6
0.6
0.6
1.3
0
0
(2)
-
-
(4)
Fast Mode
(5)
(5)
September 11, 2009
0.9
Max
400
300
300
400
50
-
-
-
-
-
-
-
-
-
-
(3)
EBU WAN PLL
Unit
KHz
µ s
µ s
µ s
µ s
µ s
µ s
µ s
pF
ns
ns
ns
ns
V
V