IDT82V3202NLG8 IDT, Integrated Device Technology Inc, IDT82V3202NLG8 Datasheet - Page 47

• Manufacturer Part Number: IDT82V3202NLG8
• Description: IC PLL WAN EBU SGL 68-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3202NLG8

• Input: CMOS
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN, 68-VFQFPN
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3202NLG8

Table 31: Register List and Map
6
ters are read or written via the microprocessor interface.
PROTECTION_CNFG is recommended to be confirmed to make sure
whether the write operation is enabled. The device provides 3 register
protection modes:
cleared by writing ‘1’.
Single-word Registers. Take the registers (04H, 05H and 06H) for an
Programming Information
IDT82V3202
Address
(Hex)
After reset, all the registers are set to their default values. The regis-
Before
Writing ‘0’ to the registers will take no effect if the registers are
The access of the Multi-word Registers is different from that of the
0A
0B
7E
0C
00
01
04
05
06
08
09
• Protected mode: no other registers can be written except register
• Fully Unprotected mode: all the writable registers can be written;
• Single Unprotected mode: one more register can be written
PROTECTION_CNFG itself;
besides register PROTECTION_CNFG. After write operation
(not including writing a ‘1’ to clear a bit to ‘0’), the device auto-
matically switches to Protected mode.
ID[7:0] - Device ID 1
ID[15:8] - Device ID 2
NOMINAL_FREQ[7:0]_CNFG - Crys-
tal Oscillator Frequency Offset Calibra-
tion Configuration 1
NOMINAL_FREQ[15:8]_CNFG - Crys-
tal Oscillator Frequency Offset Calibra-
tion Configuration 2
NOMINAL_FREQ[23:16]_CNFG
Crystal Oscillator Frequency Offset
Calibration Configuration 3
PHASE_ALARM_TIME_OUT_CNFG -
Phase Lock Alarm Time-Out Configu-
ration
INPUT_MODE_CNFG - Input Mode
Configuration
DIFFERENTIAL_IN_OUT_OSCI_CNF
G - Differential Input / Output Port &
Master Clock Configuration
MON_SW_PBO_CNFG - Frequency
Monitor, Input Clock Selection & PBO
Control
PROTECTION_CNFG - Register Pro-
tection Mode Configuration
INTERRUPT_CNFG - Interrupt Config-
uration
PROGRAMMING INFORMATION
any
Register Name
write
operation,
the
-
FREQ_MO
AUTO_EX
T_SYNC_
MULTI_FACTOR[1:0]
N_CLK
Bit 7
EN
value
-
-
EXT_SYN
G_TO_TD
LOS_FLA
in
C_EN
Bit 6
O
-
-
Global Control Registers
register
Interrupt Registers
ULTR_FAS
PH_ALAR
M_TIMEO
T_SW
Bit 5
UT
47
-
-
NOMINAL_FREQ_VALUE[23:16]
example, the write operation for the Multi-word Registers follows a fixed
sequence. The register (04H) is configured first and the register (06H) is
configured last. The three registers are configured continuously and
should not be interrupted by any operation. The crystal calibration con-
figuration will take effect after all the three registers are configured. Dur-
ing read operation, the register (04H) is read first and the register (06H)
is read last. The crystal calibration reading should be continuous and not
be interrupted by any operation.
Reserved. To ensure proper and predictable operation, bits designated
as Reserved should not be written by the users. In addition, their value
should be masked out from any testing or error detection methods that
are implemented.
6.1
of their addresses.
NOMINAL_FREQ_VALUE[15:8]
NOMINAL_FREQ_VALUE[7:0]
PROTECTION_DATA[7:0]
Table 31
Certain bit locations within the device register map are designated as
EXT_SW
SYNC_FREQ[1:0]
Bit 4
-
-
ID[15:8]
ID[7:0]
REGISTER MAP
is the map of all the registers, sorted in an ascending order
TIME_OUT_VALUE[5:0]
PBO_FRE
Bit 3
Z
-
-
IN_SONET
OSC_EDG
PBO_EN
_SDH
Bit 2
E
-
OUT1_PE
CL_LVDS
HZ_EN
Bit 1
-
-
September 11, 2009
REVERTIV
FREQ_MO
N_HARD_
E_MODE
INT_POL
Bit 0
EN
-
EBU WAN PLL
Reference
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