IDT82V3202NLG8 IDT, Integrated Device Technology Inc, IDT82V3202NLG8 Datasheet - Page 10

• Manufacturer Part Number: IDT82V3202NLG8
• Description: IC PLL WAN EBU SGL 68-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3202NLG8

• Input: CMOS
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN, 68-VFQFPN
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3202NLG8

DESCRIPTION
chronous Equipment Timing Source for Stratum 3, SMC, 4E and 4
clocks in SONET / SDH equipments, DWDM and Wireless base station,
such as GSM, 3G, DSL concentrator, Router and Access Network appli-
cations.
clock from STM-N or OC-n, PDH network synchronization timing and
external synchronization reference timing.
ing. The DPLL supports three primary operating modes: Free-Run,
Locked and Holdover. In Free-Run mode, the DPLL refers to the master
clock. In Locked mode, the DPLL locks to the selected input clock. In
Holdover mode, the DPLL resorts to the frequency data acquired in
Locked mode. Whatever the operating mode is, the DPLL gives a stable
Description
IDT82V3202
The IDT82V3202 is an integrated, single-chip solution for the Syn-
The device supports three types of input clock sources: recovered
An input clock is automatically or manually selected for DPLL lock-
10
performance without being affected by operating conditions or silicon
process variations.
device will be in a better jitter/wander performance.
Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different set-
tings cover all SONET / SDH clock synchronization requirements.
cations. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
gramming interface.
If the DPLL outputs are processed by T0/T4 APLL, the outputs of the
The device provides programmable DPLL bandwidths: 0.1 Hz to 560
A high stable input is required for the master clock in different appli-
All the read/write registers are accessed only through an I
The device can be used typically in Line Card application.
September 11, 2009
EBU WAN PLL
2
C pro-