IDT82V3202NLG8 IDT, Integrated Device Technology Inc, IDT82V3202NLG8 Datasheet - Page 32

• Manufacturer Part Number: IDT82V3202NLG8
• Description: IC PLL WAN EBU SGL 68-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3202NLG8

• Input: CMOS
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN, 68-VFQFPN
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3202NLG8

phase locked to any input clock. The frequency offset acquiring method
is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the
FAST_AVG bit, as shown in
Table 17: Frequency Offset Control in Holdover Mode
3.10.1.5.1 Automatic Instantaneous
when it enters Holdover mode. The accuracy is 4.4X10
3.10.1.5.2 Automatic Slow Averaged
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 110 minutes. The accuracy is
1.1X10
3.10.1.5.3 Automatic Fast Averaged
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 8 minutes. The accuracy is
1.1X10
3.10.1.5.4 Manual
T0_HOLDOVER_FREQ[23:0] bits. The accuracy is 1.1X10
CURRENT_DPLL_FREQ[23:0] bits.
T0_HOLDOVER_FREQ[23:0] bits. The value to be written can refer to
the value read from the CURRENT_DPLL_FREQ[23:0] bits or the
T0_HOLDOVER_FREQ[23:0] bits (refer to
Frequency Offset
tering.
Functional Description
IDT82V3202
By this method, the T0 DPLL freezes at the operating frequency
By this method, an internal IIR (Infinite Impulse Response) filter is
By this method, an internal IIR (Infinite Impulse Response) filter is
By this method, the frequency offset is set by the
The frequency offset of the T0 DPLL output is indicated by the
The device provides a reference for the value to be written to the
MAN_HOLDOVER
-5
-5
ppm.
ppm.
0
1
Read); or then be processed by external software fil-
Table
17:
AUTO_AVG
0
1
Chapter 3.10.1.5.5 Holdover
don’t-care
-8
ppm.
-5
ppm.
FAST_AVG
don’t-care
0
1
32
Table 18: Holdover Frequency Offset Read
3.10.1.5.5 Holdover Frequency Offset Read
Automatic Fast Averaged and is set by related register bits, can be read
from the T0_HOLDOVER_FREQ[23:0] bits by setting the READ_AVG
bit and the FAST_AVG bit, as shown in
3.10.1.6
selected input clock.
READ_AVG FAST_AVG
The offset value, which is acquired by Automatic Slow Averaged,
The frequency offset in ppm is calculated as follows:
In Pre-Locked2 mode, the T0 DPLL output attempts to track the
The Pre-Locked2 mode is a secondary, temporary mode.
0
1
Holdover Frequency Offset (ppm) = T0_HOLDOVER_FREQ[23:0] X
0.000011
Pre-Locked2 Mode
don’t-care The value is equal to the one written to.
0
1
Frequency Offset Acquiring Method
The value is acquired by Automatic Slow Averaged
method, not equal to the one written to.
The value is acquired by Automatic Fast Averaged
method, not equal to the one written to.
Automatic Slow Averaged
Automatic Fast Averaged
Automatic Instantaneous
T0_HOLDOVER_FREQ[23:0]
Manual
Offset Value Read from
Table
18.
September 11, 2009
EBU WAN PLL