IDT82V3202NLG8 IDT, Integrated Device Technology Inc, IDT82V3202NLG8 Datasheet - Page 59

• Manufacturer Part Number: IDT82V3202NLG8
• Description: IC PLL WAN EBU SGL 68-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3202NLG8

• Input: CMOS
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-VFQFN, 68-VFQFPN
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3202NLG8

INTERRUPTS2_STS - Interrupt Status 2
INTERRUPTS3_STS - Interrupt Status 3
Programming Information
IDT82V3202
Address: 0EH
Type: Read / Write
Default Value: 00XXXXXX
Address: 0FH
Type: Read / Write
Default Value: 1XXXXXXX
EX_SYNC_ALARM
T0_OPERATING
5 - 0
6 - 0
Bit
Bit
7
7
6
_MODE
7
7
EX_SYNC_ALARM
T0_OPERATING_MODE
T0_MAIN_REF_FAILED
Name
T0_MAIN_REF_F
-
Name
-
AILED
6
6
-
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the
EX_SYNC_ALARM_MON bit (b7, 52H).
0: Has not occurred.
1: Has occurred. (default)
This bit is cleared by writing a ‘1’.
Reserved.
This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the
T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes.
0: Has not switched. (default)
1: Has switched.
This bit is cleared by writing a ‘1’.
This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity
changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn_CMOS bit (4AH).
0: Has not failed. (default)
1: Has failed.
This bit is cleared by writing a ‘1’.
Reserved.
5
-
5
-
4
-
4
-
59
3
3
-
-
Description
Description
2
2
-
-
1
-
1
-
September 11, 2009
EBU WAN PLL
0
-
0
-