ISL12022MIBZ-T Intersil, ISL12022MIBZ-T Datasheet - Page 13

• Manufacturer Part Number: ISL12022MIBZ-T
• Description: IC RTC/CALENDAR TEMP SENS 20SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022MIBZ-T

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12022MIBZ-TCT

ADDR. SECTION
10. Crystal ALPHA at high temperature, ALPHA_H (1
11. Scratch Pad (2 bytes): Address 2Eh and 2Fh
Write capability is allowable into the RTC registers (00h
to 06h) only when the WRTC bit (bit 6 of address 08h) is
set to “1”. A multi-byte read or write operation should be
limited to one section per operation for best RTC time
keeping performance.
5. Time Stamp for V
6. Day Light Saving Time (8 bytes): 20h to 27h.
7. TEMP (2 bytes): 28h to 29h.
8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah,
9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch
0Ch
0Dh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Eh
0Fh
10h
12h
13h
14h
15h
11h
to 1Fh.
2Bh
byte): 2Dh
ALARM
CSR
RTC
TABLE 1. REGISTER MEMORY MAP (YELLOW SHADING INDICATES READ-ONLY BITS)
PWR_VBAT
PWR_VDD
NAME
ALPHA
REG
MNA0
MOA0
DWA0
FDTR
SCA0
HRA0
ITRO
BETA
FATR
DTA0
DW
MN
MO
INT
SC
HR
DT
YR
SR
DD
Status (5 bytes): Address 1Bh
13
EMOA00
IDTR01
EMNA0
EDWA0
CLRTS
ESCA0
EHRA0
EDTA0
BUSY
ARST
YR23
TSE
MIL
D
D
0
0
0
0
0
0
0
7
RESEALB
ALPHA6
SCA022
MNA022
IDTR00
WRTC
MN22
OSCF
SC22
YR22
BTSE
6
D
D
D
D
D
0
0
0
0
0
0
VB85Tp2
ALPHA5
MNA021
DSTADJ
SCA021
HRA021
FFATR5
DTA021
IATR05
MN21
BTSR
SC21
HR21
DT21
YR21
IM
5
D
D
D
0
0
0
ISL12022M
VB85Tp1
FOBATB
ALPHA4
MNA020
MOA020
SCA020
HRA020
DTA020
IATR04
BETA4
FDTR4
FATR4
MN20
MO20
SC20
HR20
DT20
YR20
ALM
4
D
D
0
A register can be read by performing a random read at
any address at any time. This returns the contents of
that register location. Additional registers are read by
performing a sequential read. For the RTC and Alarm
registers, the read instruction latches all clock registers
into a buffer, so an update of the clock does not change
the time being read. At the end of a read, the master
supplies a stop condition to end the operation and free
the bus. After a read, the address remains at the
previous address +1 so the user can execute a current
address read and continue reading the next register.
When the previous address is 2Fh, the next address will
wrap around to 00h.
It is not necessary to set the WRTC bit prior to writing
into the control and status, alarm, and user SRAM
registers.
BIT
VB85Tp0
ALPHA3
MNA013
MOA013
SCA013
HRA013
DTA013
IATR03
BETA3
FDTR3
FATR3
MN13
HR13
MO13
LVDD
SC13
DT13
YR13
FO3
3
D
D
0
V
VB75Tp2
ALPHA2
MNA012
MOA012
SCA012
HRA012
LBAT85
DTA012
IATR02
DWA02
BETA2
FDTR2
FATR2
MO12
DD
MN12
HR12
SC12
DT12
YR12
DW2
FO2
2
Trip2
V
VB75Tp1
ALPHA1
MNA011
MOA011
SCA011
HRA011
LBAT75
DTA011
DWA01
IATR01
FDTR1
BETA1
FATR1
DD
MN11
MO11
SC11
HR11
DT11
YR11
DW1
FO1
1
Trip1
V
VB75Tp0
ALPHA0
MOA010
MNA010
HRA010
SCA010
DTA010
IATR00
DWA00
BETA0
FDTR0
FATR0
DD
MO10
RTCF
SC10
MN10
HR10
YR10
DT10
DW0
FO0
0
Trip0
RANGE DEFAULT
00 to 59
00 to 59
01 to 31
01 to 12
0 to 59
0 to 59
0 to 23
1 to 31
1 to 12
0 to 99
0 to 23
0 to 6
0 to 6
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
June 4, 2010
FN6668.7
XXh
XXh
XXh
00h
00h
00h
01h
01h
00h
00h
01h
01h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h