ISL12022MIBZ-T Intersil, ISL12022MIBZ-T Datasheet - Page 16

• Manufacturer Part Number: ISL12022MIBZ-T
• Description: IC RTC/CALENDAR TEMP SENS 20SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022MIBZ-T

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12022MIBZ-TCT

Example - When the LBAT75 is Set to “1” in Battery
Mode:
The minute register changes to 30h when the device is in
battery mode, the LBAT75 is set to “1” the next time the
device switches back to Normal Mode.
Example - When the LBAT75 Remains at “0” in
Battery Mode:
If the device enters into battery mode after the minute
register reaches 49h and switches back to Normal Mode
before minute register reaches 50h, then the LBAT75 bit
will remain at “0” the next time the device switches
back to Normal Mode.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a
read only bit that is set by hardware (ISL12022M
internally) when the device powers up after having lost
all power (defined as V
is set regardless of whether V
The loss of only one of the supplies does not set the RTCF
bit to “1”. The first valid write to the RTC section after a
complete power failure resets the RTCF bit to “0” (writing
one byte is sufficient).
Interrupt Control Register (INT)
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM,
LVDD, LBAT85, and LBAT75 status bits only. When ARST
bit is set to “1”, these status bits are reset to “0” after a
valid read of the respective status register (with a valid
STOP condition). When the ARST is cleared to “0”, the
user must manually reset the ALM, LVDD, LBAT85, and
LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this
bit is “0”. Upon initialization or power-up, the WRTC must
be set to “1” to enable the RTC. Upon the completion of a
valid write (STOP), the RTC starts counting. The RTC
internal 1Hz signal is synchronized to the STOP condition
during a valid write cycle.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will
operate in the interrupt mode, where an active low pulse
width of 250ms will appear at the IRQ/F
the RTC is triggered by the alarm, as defined by the
alarm registers (0Ch to 11h). When the IM bit is cleared
to “0”, the alarm will operate in standard mode, where
the IRQ/F
is cleared to “0”.
ADDR
08h
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ARST WRTC
OUT
7
pin will be set low until the ALM status bit
6
DD
IM
5
16
= 0V and V
FOBATB FO3 FO2 FO1 FO0
DD
4
or V
BAT
BAT
3
OUT
is applied first.
= 0V). The bit
2
pin when
1
ISL12022M
0
FREQUENCY OUTPUT AND INTERRUPT BIT
(FOBATB)
This bit enables/disables the IRQ/F
battery backup mode (i.e. V
When the FOBATB is set to “1”, the IRQ/F
disabled during battery backup mode. This means that
both the frequency output and alarm output functions
are disabled. When the FOBATB is cleared to “0”, the
IRQ/F
Note that the open drain IRQ/F
pull-up to the battery voltage to operate in battery
backup mode.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function
and select the output frequency at the IRQ/F
See Table 5 for frequency selection. Default for the
ISL12022M is
FO<3:0> = 1h, or 32.768kHz output (F
When the frequency mode is enabled, it will override
the alarm mode at the IRQ/F
FREQUENCY,
TABLE 5. FREQUENCY SELECTION OF IRQ/F
32768
F
IM BIT
4096
1024
1/16
1/32
1/2
1/4
1/8
OUT
OUT
64
32
16
0
8
4
2
1
0
1
pin is enabled during battery backup mode.
UNITS
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By
Alarm
INTERRUPT/ALARM FREQUENCY
TABLE 4.
FO3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BAT
OUT
OUT
power source active).
FO2
pin.
OUT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
pin will need a
pin during
OUT
OUT
FO1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
is ON).
OUT
pin is
OUT
June 4, 2010
FN6668.7
FO0
pin.
PIN
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1