ISL12022MIBZ-T Intersil, ISL12022MIBZ-T Datasheet - Page 15

• Manufacturer Part Number: ISL12022MIBZ-T
• Description: IC RTC/CALENDAR TEMP SENS 20SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022MIBZ-T

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12022MIBZ-TCT

Control and Status Registers
(CSR)
Addresses [07h to 0Fh]
The Control and Status Registers consist of the Status
Register, Interrupt and Alarm Register, Analog Trimming
and Digital Trimming Registers.
STATUS REGISTER (SR)
The Status Register is located in the memory map at
address 07h. This is a volatile register that provides
either control or status of RTC failure (RTCF), Battery
Level Monitor (LBAT85, LBAT75), alarm trigger, Daylight
Saving Time, crystal oscillator enable and temperature
conversion in progress bit.
BUSY BIT (BUSY)
Busy Bit indicates temperature sensing is in progress. In
this mode, Alpha, Beta and ITRO registers are disabled
and cannot be accessed.
OSCILLATOR FAIL BIT (OSCF)
Oscillator Fail Bit indicates that the oscillator has
stopped.
DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)
DSTADJ is the Daylight Saving Time Adjusted Bit. It
indicates the daylight saving time forward adjustment
has happened. If a DST Forward event happens,
DSTADJ will be set to “1”. The DSTADJ bit will stay high
when DSTFD event happens, and will be reset to “0”
when the DST Reverse event happens.
DSTADJ can be set to “1” for instances where the RTC
device is initialized during the DST Forward period. The
DSTE bit must be enabled when the RTC time is more
than one hour before the DST Forward or DST Reverse
event time setting, or the DST event correction will not
happen.
DSTADJ is reset to “0” upon power-up. It will reset to “0”
when the DSTE bit in Register 15h is set to “0” (DST
disabled), but no time adjustment will happen.
ALARM BIT (ALM)
This bit announces if the alarm matches the real time
clock. If there is a match, the respective bit is set to “1”.
This bit can be manually reset to “0” by the user or
automatically reset by enabling the auto-reset bit (see
ARST bit). A write to this bit in the SR can only set it to
“0”, not “1”. An alarm bit that is set by an alarm
occurring during an SR read operation will remain set
after the read operation is complete.
ADDR
07h
BUSY
7
TABLE 2. STATUS REGISTER (SR)
OSCF DSTDJ
6
5
15
ALM
4
LVDD LBAT85 LBAT75 RTCF
3
2
1
ISL12022M
0
LOW V
This bit indicates when V
pre-selected trip level (Brownout Mode). The trip points
for the brownout levels are selected by three bits: VDD
Trip2, VDD Trip1 and VDD Trip0 in PWR_ VDD registers.
The LVDD detection is only enabled in VDD mode and
the detection happens in real time. The LVDD bit is set
whenever the V
trip level, and self clears whenever the V
pre-selected trip level.
LOW BATTERY INDICATOR 85% BIT (LBAT85)
In Normal Mode (V
battery level has dropped below the pre-selected trip
levels. The trip points are selected by three bits:
VB85Tp2, VB85Tp1 and VB85Tp0 in the PWR_VBAT
registers. The LBAT85 detection happens automatically
once every minute when seconds register reaches 59.
The detection can also be manually triggered by setting
the TSE bit in BETA register to “1”. The LBAT85 bit is set
when the V
level, and will self clear when the V
pre-selected trip level at the next detection cycle either
by manual or automatic trigger.
In Battery Mode (V
entered into battery mode by polling once every 10
minutes. The LBAT85 detection happens automatically
once when the minute register reaches x9h or x0h
minutes.
Example - When the LBAT85 is Set To “1” In
Battery Mode:
The minute the register changes to 19h when the device
is in battery mode, the LBAT85 is set to “1” the next time
the device switches back to Normal Mode.
Example - When the LBAT85 Remains at “0” In
Battery Mode:
If the device enters into battery mode after the minute
register reaches 20h and switches back to Normal Mode
before the minute register reaches 29h, then the LBAT85
bit will remain at “0” the next time the device switches
back to Normal Mode.
LOW BATTERY INDICATOR 75% BIT (LBAT75)
In Normal Mode (V
battery level has dropped below the pre-selected trip
levels. The trip points are selected by three bits:
VB75Tp2, VB75Tp1 and VB75Tp0 in the PWR_VBAT
registers. The LBAT75 detection happens automatically
once every minute when seconds register reaches 59.
The detection can also be manually triggered by setting
the TSE bit in BETA register to “1”. The LBAT75 bit is set
when the V
level, and will self clear when the V
pre-selected trip level at the next detection cycle either
by manual or automatic trigger.
In Battery Mode (V
entered into battery mode by polling once every
10 minutes. The LBAT85 detection happens
automatically once when the minute register reaches x9h
or x0h minutes.
DD
BAT
BAT
INDICATOR BIT (LVDD)
has dropped below the pre-selected trip
has dropped below the pre-selected trip
DD
DD
BAT
DD
BAT
has dropped below the pre-selected
), this bit indicates when the
), this bit indicates when the
), this bit indicates the device has
), this bit indicates the device has
DD
has dropped below the
BAT
BAT
is above the
is above the
DD
is above the
June 4, 2010
FN6668.7