ISL12022MIBZ-T Intersil, ISL12022MIBZ-T Datasheet - Page 17

• Manufacturer Part Number: ISL12022MIBZ-T
• Description: IC RTC/CALENDAR TEMP SENS 20SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022MIBZ-T

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12022MIBZ-TCT

Power Supply Control Register (PWR_VDD)
CLEAR TIME STAMP BIT (CLRTS)
This bit clears Time Stamp V
Time Stamp Battery to V
default setting is 0 (CLRTS = 0) and the Enabled setting
is 1 (CLRTS = 1).
V
(V
These bits set the trip level for the V
that V
the LVDD bit in the Status Register is set to “1”. See
Table 6.
Battery Voltage Trip Voltage Register
(PWR_VBAT)
This register controls the trip points for the two V
alarms, with levels set to approximately 85% and 75% of
the nominal battery level.
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting the V
pin from the internal circuitry. Setting this bit allows the
device to disconnect the battery and eliminate standby
current drain while the device is unused. Once V
powered up, this bit is reset and the V
connected to the internal circuitry.
The application for this bit involves placing the chip on a
board with a battery and testing the board. Once the
board is tested and ready to ship, it is desirable to
disconnect the battery to keep it fresh until the board or
unit is placed into final use. Setting RESEALB = “1”
initiates the battery disconnect, and after V
cycled down and up again, the RESEAL bit is cleared
to “0”.
09h
0Ah
ADDR
ADDR
DD
V
DD
DD
BROWNOUT TRIP VOLTAGE BITS
TRIP<2:0>)
DD
Trip2
0
0
0
0
1
1
CLRTS
D RESEALB VB85
7
has dropped below a preset level. In this event,
7
TABLE 6. V
6
6
0
V
DD
5
0
Trip1
0
0
1
1
0
0
Tp2
5
TABLE 7.
4
0
DD
DD
17
VB85
Tp1
3
0
TRIP LEVELS
Registers (TSB2V). The
DD
4
V
DD
V
to Battery (TSV2B) and
DD
VB85
Tp0
Trip0
0
1
0
1
0
1
2
Trip2 V
3
DD
BAT
alarm, indicating
VB75
Tp2
2
DD
pin is then
DD
1
VOLTAGE
Trip1 V
VB75
Tp1
2.295
2.550
2.805
3.060
4.250
4.675
TRIP
power is
(V)
1
DD
BAT
ISL12022M
DD
VB75
Tp0
is
0
Trip0
BAT
0
BATTERY LEVEL MONITOR TRIP BITS (VB85TP
<2:0>)
Three bits select the first alarm (85% of Nominal V
level for the battery voltage monitor. There are total of
7 levels that could be selected for the first alarm. Any of
the of levels could be selected as the first alarm with no
reference as to nominal Battery voltage level. See
Table 8.
BATTERY LEVEL MONITOR TRIP BITS (VB75TP
<2:0>)
Three bits select the second alarm (75% of Nominal
V
total of 7 levels that could be selected for the second
alarm. Any of the of levels could be selected as the
second alarm with no reference as to nominal Battery
voltage level. See Table 9.
Initial AT and DT Setting Register (ITRO)
These bits are used to trim the initial error (at room
temperature) of the crystal. Both Digital Trimming (DT)
and Analog Trimming (AT) methods are available. The
digital trimming uses clock pulse skipping and insertion
for frequency adjustment. Analog trimming uses load
capacitance adjustment to pull the oscillator frequency. A
range of +62.5ppm to -61.5ppm is possible with
combined digital and analog trimming.
Initial values for the ITR0 register are preset internally
and recalled to RAM registers on power-up. These
values are pre-set in device production and are
READ-ONLY. They cannot be overwritten by the
VB85Tp2
BAT
VB75Tp2
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS
) level for the battery voltage monitor. There are
0
0
0
0
1
1
1
0
0
0
0
1
1
1
(VB75TP <2:0>)
TABLE 8. VB85T ALARM LEVEL
VB85Tp1
VB75Tp1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
VB85Tp0
VB75Tp0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
BATTERY ALARM
BATTERY ALARM
TRIP LEVEL
TRIP LEVEL
2.125
2.295
2.550
2.805
3.060
4.250
4.675
1.875
2.025
2.250
2.475
2.700
3.750
4.125
(V)
(V)
June 4, 2010
FN6668.7
BAT
)