ISL12022MIBZ-T Intersil, ISL12022MIBZ-T Datasheet - Page 21

• Manufacturer Part Number: ISL12022MIBZ-T
• Description: IC RTC/CALENDAR TEMP SENS 20SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022MIBZ-T

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12022MIBZ-TCT

registers. Any one alarm register, multiple registers, or
all registers can be enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
• Single Event Mode is enabled by setting the bit 7
• Interrupt Mode is enabled by setting the bit 7 on
To clear a single event alarm, the ALM bit in the status
register must be set to “0” with a write. Note that if the
ARST bit is set to 1 (address 08h, bit 7), the ALM bit will
automatically be cleared when the status register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
• Alarm set with single interrupt (IM = “0”)
• A single alarm will occur on January 1 at 11:30 a.m.
• Set Alarm registers as follows:
After these registers are set, an alarm will be generated
when the RTC advances to exactly 11:30 a.m. on
January 1 (after seconds changes from 59 to 00) by
setting the ALM bit in the status register to “1” and also
bringing the IRQ/F
REGISTER
on any of the Alarm registers (ESCA0... EDWA0) to
“1”, the IM bit to “0”, and disabling the frequency
output. This mode permits a one-time match
between the Alarm registers and the RTC registers.
Once this match occurs, the ALM bit is set to “1” and
the IRQ/F
remain low until the ALM bit is reset. This can be
done manually or by using the auto-reset feature.
any of the Alarm registers (ESCA0... EDWA0) to “1”,
the IM bit to “1”, and disabling the frequency output.
The IRQ/F
an alarm occurs. This means that once the interrupt
mode alarm is set, it will continue to alarm for each
occurring match of the alarm and present time. This
mode is convenient for hourly or daily hardware
interrupts in microcontroller applications such as
security cameras or utility meter reading.
ALARM
DWA0
MNA0
MOA0
SCA0
HRA0
DTA0
OUT
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
OUT
output will be pulled low and will
output will now be pulsed each time
OUT
output low.
BIT
21
00h Seconds disabled
B0h Minutes set to
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
30, enabled
enabled
enabled
enabled
disabled
DESCRIPTION
ISL12022M
Example 2
• Pulsed interrupt once per minute (IM = “1”)
• Interrupts at one minute intervals when the seconds
• Set Alarm registers as follows:
Once the registers are set, the following waveform will be
seen at IRQ/F
Note that the status register ALM bit will be set each time
the alarm is triggered, but does not need to be read or
cleared.
Time Stamp V
(TSV2B)
The TSV2B Register bytes are identical to the RTC
register bytes, except they do not extend beyond the
Month. The Time Stamp captures the FIRST V
Battery Voltage transition time, and will not update upon
subsequent events until cleared (only the first event is
captured before clearing). Set CLRTS = 1 to clear this
register (Add 09h, PWR_V
Note that the time stamp registers are cleared to all “0”,
including the month and day, which is different from the
RTC and alarm registers (those registers default to 01h).
This is the indicator that no time stamping has occurred
since the last clear or initial power-up. Once a time
stamp occurs, there will be a non-zero time stamp.
Time Stamp Battery to V
(TSB2V)
The Time Stamp Battery to VDD Register bytes are
identical to the RTC register bytes, except they do not
extend beyond Month. The Time Stamp captures the
LAST transition of VBAT to VDD (only the last event of a
series of power-up/power-down events is retained). Set
CLRTS = 1 to clear this register (Add 09h, PWR_V
register).
REGISTER
register is at 30 seconds.
ALARM
MNA0
MOA0
DWA0
HRA0
SCA0
DTA0
RTC AND ALARM REGISTERS ARE BOTH “30s”
FIGURE 14. IRQ/F
7 6 5 4 3 2 1 0 HEX
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
0 0 0 0 0 0 0 0 00h Minutes disabled
0 0 0 0 0 0 0 0 00h Hours disabled
0 0 0 0 0 0 0 0 00h Date disabled
0 0 0 0 0 0 0 0 00h Month disabled
0 0 0 0 0 0 0 0 00h Day of week disabled
OUT
:
DD
to Battery Registers
BIT
DD
60s
register).
OUT
DD
WAVEFORM
Registers
enabled
DESCRIPTION
DD
June 4, 2010
to
DD
FN6668.7