ISL12022MIBZ-T Intersil, ISL12022MIBZ-T Datasheet - Page 26

• Manufacturer Part Number: ISL12022MIBZ-T
• Description: IC RTC/CALENDAR TEMP SENS 20SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022MIBZ-T

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12022MIBZ-TCT

“read” section. For a random read of the Control/Status
Registers, the slave byte must be “1101111x” in both
places.
FIGURE 18. SLAVE ADDRESS, WORD ADDRESS, AND
Write Operation
A Write operation requires a START condition, followed by
a valid Identification Byte, a valid Address Byte, a Data
Byte, and a STOP condition. After each of the three
bytes, the ISL12022M responds with an ACK. At this
time, the I
Read Operation
A Read operation consists of a three byte instruction,
followed by one or more Data Bytes (see Figure 20).
The master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
bit set to “0”, an Address Byte, a second START, and a
second Identification byte with the R/W bit set to “1”.
After each of the three bytes, the ISL12022M responds
with an ACK. Then the ISL12022M transmits Data Bytes
as long as the master responds with an ACK during the
SCL cycle following the eighth bit of each byte. The
master terminates the read operation (issuing a STOP
condition) following the last bit of the last Data Byte
(see Figure 20).
The Data Bytes are from the memory location indicated
by an internal pointer. This pointer’s initial value is
determined by the Address Byte in the Read operation
instruction, and increments by one during transmission
of each Data Byte. After reaching the memory location
2Fh, the pointer “rolls over” to 00h, and the device
continues to output data for each ACK received.
Application Section
Battery Backup Details
The ISL12022M has automatic switchover to battery
backup when the V
threshold. A wide variety of backup sources can be used,
including standard and rechargeable lithium,
supercapacitors, or regulated secondary sources. The
serial interface is disabled in battery backup, while the
oscillator and RTC registers are operational. The SRAM
register contents are powered to preserve their contents
as well.
The input voltage range for V
keep in mind the temperature compensation only
operates for V
guaranteed to operate with a V
should be changed before discharging to that level. It is
A7
D7
1
A6
D6
1
2
C interface enters a standby state.
A5
D5
0
DATA BYTES
BAT
A4
D4
1
> 2.7V. Note that the device is not
DD
D3
A3
1
drops below the V
26
1
D2
A2
BAT
BAT
1
D1
A1
is 1.8V to 5.5V, but
< 1.8V, so the battery
R/
A0
D0
BAT
SLAVE
ADDRESS BYTE
WORD
ADDRESS
DATA BYTE
mode
ISL12022M
strongly advised to monitor the low battery indicators in
the status registers and take action to replace discharged
batteries.
If a supercapacitor is used, it is possible that it may
discharge to below 1.8V during prolonged power-down.
Once powered up, the device may lose serial bus
communications until both V
down together. To avoid that situation, including
situations where a battery may discharge deeply, the
circuit in Figure 19 can be used.
The diode, D
voltage but will protect the circuit should battery voltage
drop below 1.8V. The jumper is added as a safeguard
should the battery ever need to be disconnected from the
circuit.
The V
the data sheet spec (10V/ms) otherwise battery
switchover can be delayed, resulting in SRAM contents
corruption and oscillator operation interruption.
Some applications will require separate supplies for the
RTC V
may compromise the operation of the I
applications that do require serial bus communication
with the RTC V
pulled low during the time the RTC V
0V. Otherwise, the device may lose serial bus
communications once V
to normal operation ONLY once V
powered down together.
Layout Considerations
The ISL12022M contains a quarts crystal and requires
special handling during PC board assembly. Excessive
shock and vibrations should be avoided, especially with
automated handling equipment. Ultrasound cleaning is
not advisable as it subjects the crystal to resonance and
possible failure. See also Note 6 on page 5 in the
specifications tables, which pertains to solder reflow
effects on oscillator accuracy.
The part of the package that has NC pins from pin 1 to 5
and from pin 16 to 20 contains the crystal. Low
frequency RTC crystals are known to pick up noise very
easily if layout precautions are not followed, even
embedded within a plastic package. Most instances of
erratic clocking or large accuracy errors can be traced to
the susceptibility of the oscillator circuit to interference
from adjacent high speed clock or data lines. Careful
layout of the RTC circuit will avoid noise pickup and
insure accurate clocking.
V
TO 5.5V
DD
FIGURE 19. SUGGESTED BATTERY BACKUP CIRCUIT
0.1µF
C
= 2.7V
IN
DD
DD
negative slew rate should be limited to below
and the I
BAT
VDD
ISL12022M
DD
will add a small drop to the battery
GND
powered down, the SDA pin must be
2
VBAT
C pull-ups. This is not advised, as it
DD
is powered up, and will return
J
BAT
0.1µF
DD
C
BAT
and V
DD
BAT43W
and V
DD
D
BAT
BAT
2
ramps down to
C bus. For
BAT
are powered
+
V
are both
TO 3.2V
BAT
June 4, 2010
FN6668.7
= 1.8V