ISL12022MIBZ-T Intersil, ISL12022MIBZ-T Datasheet - Page 25

• Manufacturer Part Number: ISL12022MIBZ-T
• Description: IC RTC/CALENDAR TEMP SENS 20SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022MIBZ-T

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12022MIBZ-TCT

An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting
device, either master or slave, releases the SDA bus
after transmitting eight bits. During the ninth clock cycle,
the receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 16).
The ISL12022M responds with an ACK after recognition
of a START condition followed by a valid Identification
Byte, and once again, after successful receipt of an
Address Byte. The ISL12022M also responds with an ACK
after receiving a Data Byte of a write operation. The
master must respond with an ACK after receiving a Data
Byte of a read operation.
Device Addressing
Following a start condition, the master must output a
Slave Address Byte. The 7 MSBs are the device
identifiers. These bits are “1101111” for the RTC
registers and “1010111” for the User SRAM.
SDA OUTPUT FROM
FROM RECEIVER
TRANSMITTER
SDA OUTPUT
SCL FROM
SDA
MASTER
SCL
THE ISL12022M
SIGNAL AT SDA
SIGNALS FROM
SIGNALS FROM
FIGURE 17. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
THE MASTER
FIGURE 15. VALID DATA CHANGES, START AND STOP CONDITIONS
25
START
START
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
S
T
A
R
T
HIGH
1
IDENTIFICATION
1
1
0
BYTE
1
STABLE
1 1 1
ISL12022M
DATA
0
A
K
C
WRITE
CHANGE
DATA
0 0 0 0
The last bit of the Slave Address Byte defines a read or
write operation to be performed. When this R/W bit is a
“1”, a read operation is selected. A “0” selects a write
operation (refer to Figure 18).
After loading the entire Slave Address Byte from the SDA
bus, the ISL12022M compares the device identifier and
device select bits with “1101111” or “1010111”. Upon a
correct compare, the device outputs an acknowledge on
the SDA line.
Following the Slave Byte is a one byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up, the
internal address counter is set to address 00h, so a
current address read starts at address 00h. When
required, as part of a random read, the master must
supply the 1 Word Address Bytes, as shown in Figure 20.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
ADDRESS
BYTE
STABLE
DATA
8
A
C
K
DATA
BYTE
HIGH IMPEDANCE
STOP
ACK
9
A
C
K
O
S
T
P
June 4, 2010
FN6668.7