HYB 39S128160CE-7.5 Infineon Technologies, HYB 39S128160CE-7.5 Datasheet - Page 12

• Manufacturer Part Number: HYB 39S128160CE-7.5
• Manufacturer: Infineon Technologies
• Type: SDRAMr

Specifications of HYB 39S128160CE-7.5

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 100mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

INFINEON Technologies
once the burst length has been reached. In other words, unlike burst length of 2, 4, and 8, full page
burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and precharge operations on two or
more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages.
Burst Length and Sequence
Burst
Length
2
4
8
Full Page
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any
refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word line after the refresh and no external precharge
(A2 A1 A0)
Address
Starting
000
001
010
011
100
101
110
111
nnn
xx0
xx1
x00
x01
x10
x11
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
Cn, Cn+1, Cn+2....
Sequential Burst
Addressing
2
3
4
5
6
7
0
1
(decimal)
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
3
4
5
6
7
0
1
2
0, 1
1, 0
4
5
6
7
0
1
2
3
12
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
128-MBit Synchronous DRAM
HYB 39S128400/800/160CT(L)
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
Interleave Burst
not supported
Addressing
2
3
0
1
6
7
4
5
(decimal)
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
3
2
1
0
7
6
5
4
0, 1
1, 0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
t
RAS
6
7
4
5
2
3
0
1
or the
7
6
5
4
3
2
1
0
9.01