MT45W256KW16BEGB-708 WT Micron Technology Inc, MT45W256KW16BEGB-708 WT Datasheet - Page 13

• Manufacturer Part Number: MT45W256KW16BEGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W256KW16BEGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 8:
PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5
8mb_4mb_burst_cr1_0_p22z__2.fm - Rev. B 4/ 08 EN
DQ[15:0]
Burst Mode READ (4-Word Burst)
LB#/UB#
A[17:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
Note:
The WAIT output will be asserted as soon as CE# goes LOW and will be deasserted to
indicate when data is to be transferred into or out of the memory. WAIT will again be
asserted if the burst crosses the boundary between 128-word rows. When the Cellu-
larRAM device has restored the previous row’s data and accessed the next row, WAIT will
be de-asserted and the burst can continue (see Figure 35 on page 43).
By suspending burst mode, the processor can access other devices without incurring the
timing penalty of the initial latency for a new burst. Bursts are suspended by stopping
CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the
burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs;
otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active,
and, as a result, no other devices should directly share the WAIT connection to the
controller. To continue the burst sequence, OE# is taken LOW, and then CLK is restarted
after valid data is available on the bus.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than
will cause CE# to remain LOW for longer than
burst restarted with a new CE# LOW/ADV# LOW cycle.
READ burst identified
Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during
delay.
t
(WE# = HIGH)
CEM unless row boundaries are crossed at least every
address
Valid
4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory
Latency code 2 (3 clocks)
13
D[0]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[1]
t
CEM, CE# should be taken HIGH and the
Don’t Care
D[2]
t
CEM. If a burst suspension
Bus Operating Modes
©2008 Micron Technology, Inc. All rights reserved.
Undefined
D[3]