MT45W256KW16BEGB-708 WT Micron Technology Inc, MT45W256KW16BEGB-708 WT Datasheet - Page 26

• Manufacturer Part Number: MT45W256KW16BEGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W256KW16BEGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Output Impedance (BCR[5]) Default = Outputs Use Full-Drive Strength
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
Figure 20:
Figure 21:
PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5
8mb_4mb_burst_cr1_0_p22z__2.fm - Rev. B 4/ 08 EN
WAIT Configuration (BCR[8] = 0)
WAIT Configuration (BCR[8] = 1)
Note:
Note:
The output driver strength can be altered to adjust for different data bus loading
scenarios. The reduced-strength option should be more than adequate in stacked chip
(Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-
drive-strength option is included to minimize noise generated on the data bus during
READ operations. Normal output impedance should be selected when using a discrete
CellularRAM device in a more heavily loaded data bus environment. Partial drive is
approximately one-quarter-full drive strength. Outputs are configured at full-drive
strength during testing.
The WAIT configuration bit is used to determine when WAIT transitions between the
asserted and the deasserted state with respect to valid data presented on the data bus.
The memory controller will use the WAIT signal to coordinate data transfer during
synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid
on the clock edge immediately after WAIT transitions to the deasserted or asserted state,
respectively (see Figure 20 and Figure 22 on page 27). When BCR[8] = 1, the WAIT signal
transitions one clock period prior to the data bus going valid or invalid (see Figures 21
and Figure 22 on page 27).
DQ[15:0]
D[15:0]
WAIT
CLK
WAIT
Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 22 on
page 27.
Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 22
on page 27.
CLK
Data valid (or invalid) after one clock delay
High-Z
Data immediately valid (or invalid)
4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory
High-Z
Data[0]
Data[0]
Data[1]
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Configuration Registers
©2008 Micron Technology, Inc. All rights reserved.