MT45W256KW16BEGB-708 WT Micron Technology Inc, MT45W256KW16BEGB-708 WT Datasheet - Page 24

• Manufacturer Part Number: MT45W256KW16BEGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W256KW16BEGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Bus Configuration Register
Figure 19:
PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5
8mb_4mb_burst_cr1_0_p22z__2.fm - Rev. B 4/ 08 EN
Register Select
BCR[17]
A17
17
0
1
Bus Configuration Register Definition
Must be set to "0"
Select RCR
Select BCR
Reserved
Notes:
16
A16
BCR[15]
0
1
Operating
Register Select
Mode
BCR[13]
15
A15
0
0
0
0
1
1
1
1
Must be set to "0"
BCR[10]
BCR[8]
The BCR defines how the CellularRAM device interacts with the system memory bus.
Page mode operation is enabled by a bit contained in the RCR. Figure 19 defines the
control bits in the BCR. At power-up, the BCR is set to 9D4Fh.
The BCR is accessed using CRE and A[17] HIGH or through the configuration register
software sequence with DQ = 0001h on the third cycle.
1. All burst WRITEs are continuous.
Asynchronous access mode (default)
Synchronous burst access mode
0
1
0
1
Reserved
BCR[12] BCR[11]
14
0
0
1
1
0
0
1
1
A14
Operating Mode
Active LOW
Active HIGH (default)
Asserted one data cycle before delay (default)
Asserted during delay
A13
13 12 11
Counter
Latency
0
1
0
1
0
1
0
1
A12A11 A10
4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory
WAIT Polarity
Code 0–reserved
Code 1–reserved
Code 2
Code 3 (default)
Code 4–reserved
Code 5–reserved
Code 6–reserved
Code 7–reserved
WAIT Configuration
Latency Counter
Polarity
WAIT
10
Must be set to "0"
Reserved
9
A9
Configuration (WC)
24
WAIT
8
A8
BCR[6]
Must be set to "0"
0
1
Reserved
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BCR[5]
A7
7
0
1
Not supported
Rising edge (default)
BCR[3]
Configuration (CC)
1/4 drive
0
1
Full drive (default)
Output Impedance
Clock
Clock Configuration
BCR[2]
6
0
0
0
1
A6
Burst no wrap (default)
Burst wraps within the burst length
BCR[1] BCR[0]
0
1
1
1
Impedance
Configuration Registers
Output
Burst Wrap (Note 1)
5
A5
1
0
1
1
Must be set to "0"
©2008 Micron Technology, Inc. All rights reserved.
Reserved
4 words
8 words
16 words
Continuous burst (default)
A4
4
Burst Length (Note 1)
Wrap (BW)
Burst
A3
3
1
Length (BL)
2
A2 A1 A0
Burst
1
0
1