MT45W256KW16BEGB-708 WT Micron Technology Inc, MT45W256KW16BEGB-708 WT Datasheet - Page 28

• Manufacturer Part Number: MT45W256KW16BEGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W256KW16BEGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Refresh Configuration Register
Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh
Figure 24:
Deep Power-Down (RCR[4]) Default = DPD Disabled
Page Mode Operation (RCR[7]) Default = Disabled
PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5
8mb_4mb_burst_cr1_0_p22z__2.fm - Rev. B 4/ 08 EN
Register Select
RCR[17]
RCR[7]
A17
Refresh Configuration Register Mapping
0
1
17
0
1
All must be set to "0"
Notes:
Select RCR
Select BCR
Register Select
Page mode disabled (default)
Page mode enable
Page Mode Enable/Disable
Reserved
A16–A8
The refresh configuration register (RCR) defines how the CellularRAM device performs
its transparent self refresh. Altering the refresh parameters can dramatically reduce
current consumption during standby mode. Page mode control is also embedded into
the RCR. Figure 24 describes the control bits used in the RCR. At power-up, the RCR is set
to 0010h.
The RCR is accessed using CRE and A[17] LOW or through the configuration register
software-access sequence with DQ = 0000h on the third cycle (see “Configuration Regis-
ters” on page 18).
The PAR bits restrict refresh operation to a portion of the total memory array. The refresh
options are full array or none of the array.
1. Other settings result in full-array refresh coverage.
The deep power-down bit enables and disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
reenabled, the CellularRAM device will require 150µs to perform an initialization proce-
dure before normal operations can resume.
Deep power-down is enabled when RCR[4] = 0 and remains enabled until RCR[4] is set to
“1.” DPD should not be enabled or disabled with the software-access sequence; instead,
use CRE to access the RCR.
The page mode operation bit determines whether page mode is enabled for asynchro-
nous READ operations. In the power-up default state, page mode is disabled.
16–8
Page
7
A7
4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory
Must be set to "0"
Reserved
6
A6
5
A5
RCR[4]
DPD
0
1
4
28
A4
Must be set to "0"
Reserved
RCR[2]
DPD enable
DPD disable (default)
Deep Power-Down
0
1
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A3
RCR[1]
0
0
2
A2
RCR[0]
0
0
PAR
1
1
Configuration Registers
None of array
Full array (default)
A1
Refresh Coverage
©2008 Micron Technology, Inc. All rights reserved.
0
A0
Address Bus