EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 136
![IC CYCLONE III FPGA 5K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP3C5F256C8N
Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
Specifications of EP3C5F256C8N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N
EP3C5F256C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA
Quantity:
853
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
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7–12
Figure 7–7. RSDS Interface with Single Resistor Network on the Top and Bottom I/O Banks
Note to
(1)
LVPECL I/O Support in the Cyclone III Device Family
Figure 7–8. LVPECL AC-Coupled Termination
Cyclone III Device Handbook, Volume 1
R
P
Figure
= 100
Ω
7–7:
f
Cyclone III Device Family
RSDS Transmitter
Figure 7–7
bottom I/O banks.
The LVPECL I/O standard is a differential interface standard that requires a 2.5-V
V
telecommunications, data communications, and clock distribution. The Cyclone III
device family supports the LVPECL input standard at the dedicated clock input pins
only. The LVPECL receiver requires an external 100-Ω termination resistor between
the two signals at the input buffer.
For more information about the LVPECL I/O standard electrical specification, refer to
the
AC coupling is required when the LVPECL common mode voltage of the output
buffer is higher than the Cyclone III device family LVPECL input common mode
voltage.
Figure 7–8
receiver are external to the device. DC-coupled LVPECL is supported if the LVPECL
output common mode voltage is in the Cyclone III device family LVPECL input buffer
specification
CCIO.
Emulated
Cyclone III Device Data Sheet
Transmitter
LVPECL
This standard is used in applications involving video graphics,
shows the RSDS interface with a single resistor network on the top and
shows the AC-coupled termination scheme. The 50-Ω resistors used at the
(Figure
Single Resistor Network
0.1 µF
0.1 µF
7–9).
R
P
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Z 0 = 50
Z 0 = 50
and
Cyclone III LS Device Data Sheet
V ICM
50 Ω
50 Ω
50
50
100 Ω
Cyclone III Device Family
LVPECL Receiver
RSDS Receiver
© December 2009 Altera Corporation
High-Speed I/O Standards Support
chapters.
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