EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 203

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
FPP Configuration
© December 2009
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Altera Corporation
The FPP configuration in Cyclone III device family is designed to meet the increasing
demand for faster configuration time. Cyclone III device family is designed with the
capability of receiving byte-wide configuration data per clock cycle.
You can perform the FPP configuration of Cyclone III device family with an intelligent
host, such as a MAX II device or microprocessor with flash memory. If your system
already contains a CFI flash memory, you can use it for the Cyclone III device family
configuration storage as well. The MAX II PFL feature in MAX II devices provides an
efficient method to program CFI flash memory devices through the JTAG interface
and the logic to control configuration from the flash memory device to the Cyclone III
device family. Both PS and FPP configuration schemes are supported using this PFL
feature.
For more information about the PFL, refer to
with the Quartus II
Cyclone III device family does not support enhanced configuration devices for PS or
FPP configurations.
FPP configuration is not supported in the E144 package of Cyclone III devices.
FPP Configuration Using an External Host
The FPP configuration using an external host provides a fast method to configure
Cyclone III device family. In the FPP configuration scheme, you can use an external
host device to control the transfer of configuration data from a storage device, such as
flash memory, to the target Cyclone III device family. You can store configuration data
in either an .rbf, .hex, or .ttf format. When using the external host, a design that
controls the configuration process, such as fetching the data from flash memory and
sending it to the device, must be stored in the external host device.
the configuration interface connections between the Cyclone III device family and an
external device for single-device configuration.
Figure 9–20. Single-Device FPP Configuration Using an External Host
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. V
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum
enough to meet the V
refer to
overshoot equation outlined in
Figure
Table 9–7 on page
9–20:
(MAX II Device or
Microprocessor)
External Host
Software.
IH
specification of the I/O on the device and the external host.
ADDR
9–11. Connect the MSEL pins directly to V
Memory
“Configuration and JTAG Pin I/O Requirements” on page
DATA[7..0]
10 k
V CCIO (1) V CCIO (1)
10 k
GND
AN 386: Using the Parallel Flash Loader
Cyclone III Device Family
CONF_DONE
nSTATUS
nCE
DATA[7..0] (4)
nCONFIG
DCLK (4)
CCA
or GND.
MSEL[3..0]
Cyclone III Device Handbook, Volume 1
nCEO
N.C. (2)
9–7.
Figure 9–20
(3)
CC
must be high
shows
9–43