EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 173

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
1
1
Altera Corporation
Figure 9–3. Single-Device AS Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Cyclone III device family uses the ASDO-to-ASDI path to control the configuration device.
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
(5) These are dual-purpose I/O pins. The nCSO pin functions as the FLASH_NCE pin in AP mode. The ASDO pin
(6) Connect the series resistor at the near end of the serial configuration device.
When connecting a serial configuration device to a Cyclone III device family in the
single-device AS configuration, you must connect a 25-Ω series resistor at the near
end of the serial configuration device for DATA[0]. The 25-Ω resistor in the series
works to minimize the driver impedance mismatch with the board trace and reduce
overshoot seen at the Cyclone III device family DATA[0]input pin.
In a single-device AS configuration, the maximum board loading and board trace
length between the supported serial configuration device and the Cyclone III device
family must follow the recommendations in
The DCLK generated by the Cyclone III device family controls the entire configuration
cycle and provides timing for the serial interface. Cyclone III device family uses a 40-
MHz internal oscillator to generate DCLK. There are some variations in the internal
oscillator frequency because of the process, voltage, and temperature conditions in
Cyclone III device family. The internal oscillator is designed to ensure that its
maximum frequency is guaranteed to meet the EPCS device specifications.
EPCS1 does not support Cyclone III device family because of its insufficient memory
capacity.
Table 9–8
Table 9–8. AS DCLK Output Frequency
refer to
functions as the DATA[1] pin in other AP and FPP modes.
Oscillator
40 MHz
Figure
Table 9–7 on page
lists the AS DCLK output frequency for Cyclone III device family.
Serial Configuration
9–3:
Device
DCLK
DATA
ASDI
nCS
10 kΩ
Minimum
V
9–11. Connect the MSEL pins directly to V
CCIO
20
25 Ω (6)
(1)
10 kΩ
CCIO
V
CCIO
supply of the bank in which the pin resides.
(2)
(1)
10 kΩ
V
GND
CCIO
Typical
30
(1)
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
nCSO (5)
ASDO (5)
Table 9–9 on page
Cyclone III Device Family
CCA
or GND.
MSEL[3..0]
Maximum
Cyclone III Device Handbook, Volume 1
nCEO
40
9–20.
N.C. (3)
(4)
MHz
Unit
9–13