EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 270

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

12–4
Table 12–3. IEEE Std. 1149.1 (JTAG) Instructions Supported by Cyclone III Device Family (Part 2 of 2)
Cyclone III Device Handbook, Volume 1
APFC_BOOT_ADDR (2),
FACTORY
KEY_PROG_VOL
KEY_CLR_VREG
Notes to
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(2) For more information about how to use CONFIG_IO, EN_ACTIVE_CLK, DIS_ACTIVE_CLK, ACTIVE_DISENGAGE,
(3) APFC_BOOT_ADDR instruction is not supported in Cyclone III LS devices.
(4) For Cyclone III LS devices only. For more information about how to program the security key into the volatile registers, refer to the
ACTIVE_ENGAGE and APFC_BOOT_ADDR instructions for Cyclone III device family, refer to the
Remote System Upgrades in Cyclone III Devices
Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices
JTAG Instruction
Table
(4)
12–3:
1
(4)
(4)
The IEEE Std. 1149.1 BST circuitry is enabled upon device power-up. You can perform
BST on Cyclone III device family before, after, and during configuration. Cyclone III
device family supports the BYPASS, IDCODE and SAMPLE instructions during
configuration without interrupting configuration. To send all other JTAG instructions,
interrupt the configuration using the CONFIG_IO instruction except for active
configuration schemes in which the ACTIVE_DISENGAGE instruction is used instead.
The CONFIG_IO instruction allows you to configure I/O buffers via the JTAG port,
and when issued, interrupts configuration. This instruction allows you to perform
board-level testing prior to configuring Cyclone III device family. Alternatively, you
can wait for the configuration device to complete configuration. After configuration is
interrupted and JTAG BST is complete, you must reconfigure the part via JTAG
(PULSE_NCONFIG instruction) or by pulsing nCONFIG low.
When you perform JTAG boundary-scan testing before configuration, the nCONFIG
pin must be held low.
(3)
Instruction Code
10 0111 0000
10 1000 0001
01 1010 1101
00 0010 1001
chapter.
Clears the volatile verify register which signifies the validity of the
volatile keys stored in the registers. You must clear the volatile verify
register by issuing this command whenever you attempt to program a
new volatile key. This instruction must be asserted for at least 10 TCK
cycles.
Places the 22-bit active boot address register between the TDI and
TDO pins, allowing a new active boot address to be serially shifted into
TDI and into the active parallel (AP) flash controller. In remote system
upgrade, the PFC_BOOT_ADDR instruction sets the boot address for
the factory configuration.
Enables access to all other JTAG instructions (other than BYPASS,
SAMPLE/PRELOAD and EXTEST instructions, which are supported
upon power up). This instruction also clears the device configuration
data and advanced encryption standard (AES) volatile key.
Used to enter and store the security key into volatile registers. When
this instruction is executed, TDI is connected to a 512-bit volatile key
scan chain. TDO is not connected to the end of this scan chain.
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
chapter.
Description
Configuration, Design Security, and
IEEE Std. 1149.1 BST Operation Control
© December 2009 Altera Corporation