EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 16

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

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Design Security Feature
Increased System Integration
Cyclone III Device Handbook, Volume 1
Cyclone III LS devices offer the following design security features:
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Configuration security using advanced encryption standard (AES) with 256-bit
volatile key
Routing architecture optimized for design separation flow with the Quartus
software
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Ability to disable external JTAG port
Error Detection (ED) Cycle Indicator to core
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Ability to clear contents of the FPGA logic, CRAM, embedded memory, and
AES key
Internal oscillator enables system monitor and health check capabilities
High memory-to-logic and multiplier-to-logic ratio
High I/O count, low-and mid-range density devices for user I/O constrained
applications
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Four phase-locked loops (PLLs) per device provide robust clock management and
synthesis for device clock management, external system clock management, and
I/O interfaces
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Remote system upgrade without the aid of an external controller
Dedicated cyclical redundancy code checker circuitry to detect single-event upset
(SEU) issues
Nios
custom-fit embedded processing solutions
Design separation flow achieves both physical and functional isolation
between design partitions
Provides a pass or fail indicator at every ED cycle
Provides visibility over intentional or unintentional change of configuration
random access memory (CRAM) bits
Adjustable I/O slew rates to improve signal integrity
Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X,
LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS
Supports the multi-value on-chip termination (OCT) calibration feature to
eliminate variations over process, voltage, and temperature (PVT)
Five outputs per PLL
Cascadable to save I/Os, ease PCB routing, and reduce jitter
Dynamically reconfigurable to change phase shift, frequency multiplication or
division, or both, and input frequency in the system without reconfiguring the
device
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II embedded processor for Cyclone III device family, offering low cost and
Chapter 1: Cyclone III Device Family Overview
© December 2009 Altera Corporation
Cyclone III Device Family Features
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