EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 208

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

9–48
Table 9–14. FPP Timing Parameters for Cyclone III Device Family
JTAG Configuration
Cyclone III Device Handbook, Volume 1
t
t
Notes to
(1) This information is preliminary.
(2) This value is applicable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting up the device.
(4) Cyclone III EP3C5, EP3C10, EP3C16, EP3C25, and EP3C40 devices support a DCLK f
(5) For more information about the initialization clock cycles required in Cyclone III device family, refer to
CD2C U
CD2UM C
Symbol
and all the Cyclone III LS devices support a DCLK f
Table
f
9–14:
1
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR
option on
JTAG has developed a specification for boundary-scan testing. This boundary-scan
test (BST) architecture offers the capability to efficiently test components on PCBs
with tight lead spacing. The BST architecture can test pin connections without using
physical test probes and capture functional data while a device is operating normally.
You can also use the JTAG circuitry to shift configuration data into the device. The
Quartus II software automatically generates .sofs that are used for JTAG
configuration with a download cable in the Quartus II software programmer.
For more information about JTAG boundary-scan testing, refer to the
(JTAG) Boundary-Scan Testing for Cyclone III Devices
JTAG instructions have precedence over any other device configuration modes.
Therefore, JTAG configuration can take place without waiting for other configuration
modes to complete. For example, if you attempt JTAG configuration of Cyclone III
device family during PS configuration, PS configuration terminates and JTAG
configuration begins. If the Cyclone III device family MSEL pins are set to AS mode,
the Cyclone III device family does not output a DCLK signal when JTAG configuration
takes place.
The four required pins for a device operating in JTAG mode are TDI, TDO, TMS, and
TCK. The TCK pin has an internal weak pull-down resistor while the TDI and TMS pins
have weak internal pull-up resistors (typically 25 kΩ). The TDO output pin is powered
by V
JTAG pins support only LVTTL I/O standard. All user I/O pins are tri-stated during
JTAG configuration.
The TDO output is powered by the V
CCIO
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
in I/O bank 1. All the JTAG input pins are powered by the V
Parameter
MAX
Table 9–15
of 100 MHz.
lists the function of each JTAG pin.
CCIO
(Note 1)
4 × maximum DCLK period
t
cycles × CLKUSR period)
C D2CU
power supply of I/O bank 1.
+ (initialization clock
MAX
Minimum
(Part 2 of 2)
of 133 MHz. Cyclone III EP3C55, EP3C80, EP3C120
chapter.
Table 9–5 on page
© December 2009 Altera Corporation
(5)
Maximum
CCIO
Configuration Features
IEEE 1149.1
9–10.
—
—
pin. All the
Unit
—
—