EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 46
EP3C5F256C8N
Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
Specifications of EP3C5F256C8N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N
EP3C5F256C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA
Quantity:
853
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
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- EP3C5F256C8N PDF datasheet #4
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- EP3C10M164C8N PDF datasheet #6
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3–10
Simple Dual-Port Mode
Table 3–3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode)
Cyclone III Device Handbook, Volume 1
8192 × 1
4096 × 2
2048 × 4
1024 × 8
512 × 16
256 × 32
1024 × 9
512 × 18
256 × 36
Read Port
8192
v
v
v
v
v
v
—
—
—
× 1
Simple dual-port mode supports simultaneous read and write operations to different
locations.
Figure 3–9. Cyclone III Device Family Simple Dual-Port Memory
Note to
(1) Simple dual-port RAM supports input or output clock mode in addition to the read or write clock mode shown.
Cyclone III device family M9K memory blocks support mixed-width configurations,
allowing different read and write port widths.
Table 3–3
In simple dual-port mode, M9K memory blocks support separate wren and rden
signals. You can save power by keeping the rden signal low (inactive) when not
reading. Read-during-write operations to the same address can either output “Don’t
Care” data at that location or output “Old Data”. To choose the desired behavior, set
the Read-During-Write option to either Don’t Care or Old Data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. For more information about
this behavior, refer to
4096
v
v
v
v
v
v
—
—
—
Figure
× 2
lists mixed-width configurations.
Figure 3–9
3–9:
2048
v
v
v
v
v
v
—
—
—
× 4
shows the simple dual-port memory configuration.
“Read-During-Write Operations” on page
1024
v
v
v
v
v
v
—
—
—
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
× 8
Write Port
512
v
v
v
v
v
v
—
—
—
× 16
Chapter 3: Memory Blocks in the Cyclone III Device Family
256
rd_addressstall
v
v
v
v
v
v
—
—
—
rdaddress[ ]
× 32
rdclocken
rdclock
rden
q[ ]
1024
© December 2009 Altera Corporation
(Note 1)
v
v
v
—
—
—
—
—
—
× 9
3–16.
512
v
v
v
—
—
—
—
—
—
× 18
Memory Modes
256
—
—
—
—
—
—
v
v
v
× 36
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