EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 190
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EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX150CF23I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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8–24
Cyclone IV Device Handbook, Volume 1
Default read mode of the supported parallel flash memory and all writes to the
parallel flash memory are asynchronous. Both the parallel flash families support a
synchronous read mode, with data supplied on the positive edge of DCLK.
The serial clock (DCLK) generated by Cyclone IV E devices controls the entire
configuration cycle and provides timing for the parallel interface.
Multi-Device AP Configuration
You can configure multiple Cyclone IV E devices using a single parallel flash. You can
cascade multiple Cyclone IV E devices using the chip-enable (nCE) and
chip-enable-out (nCEO) pins. The first device in the chain must have its nCE pin
connected to GND. You must connect its nCEO pin to the nCE pin of the next device in
the chain. Use an external 10-k pull-up resistor to pull the nCEO signal high to its
V
its configuration data from the bitstream, it drives the nCEO pin low, enabling the next
device in the chain. You can leave the nCEO pin of the last device unconnected or use
it as a user I/O pin after configuration if the last device in the chain is a Cyclone IV E
device. The nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA[15..8], and
DATA[7..0] pins of each device in the chain are connected
and
The first Cyclone IV E device in the chain, as shown in
Figure 8–9 on page
configuration of the entire chain. You must connect its MSEL pins to select the AP
configuration scheme. The remaining Cyclone IV E devices are used as configuration
slaves. You must connect their MSEL pins to select the FPP configuration scheme. Any
other Altera device that supports FPP configuration can also be part of the chain as a
configuration slave.
The following are the configurations for the DATA[15..0] bus in a multi-device AP
configuration:
■
■
CCIO
Byte-wide multi-device AP configuration
Word-wide multi-device AP configuration
Figure 8–9 on page
level to help the internal weak pull-up resistor. When the first device captures all
8–26, is the configuration master device and controls the
8–26).
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Figure 8–8 on page 8–25
© December 2010 Altera Corporation
(Figure 8–8 on page 8–25
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