EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 266
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EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX150CF23I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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11–2
Table 11–1. Power Supply Descriptions for the Cyclone IV GX Devices (Part 2 of 2)
Hot-Socketing Specifications
Devices Driven Before Power-Up
I/O Pins Remain Tri-stated During Power-Up
Cyclone IV Device Handbook, Volume 1
VCCL_GXB
Notes to
(1) You must power up VCCA even if the phase-locked loop (PLL) is not used.
(2) I/O banks 3, 8, and 9 contain configuration pins. You can only power up the V
(3) All device packages of EP4CGX15, EP4CGX22, and device package F169 and F324 of EP4CGX30 devices have two VCC_CLKIN dedicated
(4) You must set VCC_CLKIN to 2.5 V if the CLKIN is used as high-speed serial interface (HSSI) refclk. VCC_CLKIN located at I/O banks
For Fast Passive Parallel (FPP) configuration mode, you must power up the V
clock input I/O located at Banks 3A and 8A. Device package F484 of EP4CGX30, all device packages of EP4CGX50, EP4CGX75, EP4CGX110,
and EP4CGX150 devices have four VCC_CLKIN dedicated clock input I/O bank located at banks 3A, 3B, 8A, and 8B.
3B and 8B only support a nominal voltage level of 2.5 V for LVDS input function because they are dedicated for HSSI refclk. For EP4CGX50,
EP4CGX75, EP4CGX110, and EP4CGX150 devices, the single-ended input CLK support is available for dedicated input CLK pins at I/O banks
3B and 8B.
Power Supply Pin
Table
11–1:
Table 11–2. Power Supply Descriptions for the Cyclone IV E Devices
Cyclone IV devices are hot-socketing compliant without the need for any external
components or special design requirements. Hot-socketing support in Cyclone IV
devices has the following advantages:
■
■
You can drive signals into regular Cyclone IV E I/O pins and transceiver
Cyclone IV GX I/O pins before or during power up or power down without
damaging the device. Cyclone IV devices support any power-up or power-down
sequence to simplify system-level designs.
The output buffers of Cyclone IV devices are turned off during system power up or
power down. Cyclone IV devices do not drive out until the device is configured and
working in recommended operating conditions. The I/O pins are tri-stated until the
device enters user mode.
VCCINT
VCCA
VCCD_PLL
VCCIO
Notes to
(1) You must power up VCCA even if the PLL is not used.
(2) I/O banks 1, 6, 7, and 8 contain configuration pins.
You can drive the device before power up without damaging the device.
I/O pins remain tri-stated during power up. The device does not drive out before
or during power-up. Therefore, it does not affect other buses in operation.
Power Supply Pin
(1)
Table
(2)
Nominal Voltage Level (V)
11–2:
1.2
Nominal Voltage Level (V)
1.2, 1.5, 1.8, 2.5, 3.0, 3.3
Transceiver PMA and auxiliary power supply
CCIO
CCIO
1.0, 1.2
1.0, 1.2
level of I/O banks 3 and 9 to 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V.
2.5
level of I/O bank 8 to 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V.
Chapter 11: Power Requirements for Cyclone IV Devices
Description
Core voltage power supply
PLL analog power supply
PLL digital power supply
I/O banks power supply
© July 2010 Altera Corporation
Hot-Socketing Specifications
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