EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 310
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EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX150CF23I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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1–30
Cyclone IV Device Handbook, Volume 2
Figure 1–32. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F484 and
Larger Packages
Notes to
(1) High-speed clock.
(2) Low-speed clock.
(3) These PLLs have restricted clock driving capability and may not reach all connected channels. For details, refer to
The transceiver datapath clocking varies in non-bonded channel configuration
depending on the PCS configuration.
Figure 1–33
each channel selects the high- and low-speed clock from one of the supported PLLs.
The high-speed clock feeds to the serializer for parallel to serial operation. The
low-speed clock feeds to the following blocks in the transmitter PCS:
■
■
■
When the byte serializer is enabled, the low-speed clock frequency is halved before
feeding into the read clock of TX phase compensation FIFO. The low-speed clock is
available in the FPGA fabric as tx_clkout port, which can be used in the FPGA
fabric to send transmitter data and control signals.
8B/10B encoder
read clock of the byte serializer
read clock of the TX phase compensation FIFO
Table
Figure 1–32
1–9.
shows the datapath clocking in transmitter only operation. In this mode,
:
Transceiver
Transceiver
GXBL1
GXBL0
Block
Block
Ch3
Ch2
Ch1
Ch0
Ch3
Ch2
Ch1
Ch0
MPLL_8
MPLL_7
MPLL_6
MPLL_5
(3)
(3)
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
TX PMA
(2)
(2)
(1)
Chapter 1: Cyclone IV Transceivers Architecture
(1)
Not applicable in
F484 package
GPLL_2
GPLL_1
(3)
(3)
© December 2010 Altera Corporation
Transceiver Clocking Architecture
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