EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 382
EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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2–16
PCIe Functional Mode
Figure 2–10. Reset Sequence of PCIe Functional Mode
Notes to
(1) This timing diagram is drawn based on the PCIe Gen 1 ×1 mode.
(2) For bonded PCIe Gen 1 ×2 and ×4 modes, there will be additional rx_freqlocked[n] signal. n=number of channels.
(3) For t
(4) For t
(5) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
Cyclone IV Device Handbook, Volume 2
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
LTD_Manual
LTD_Auto
Figure
Reset / Power Down Signals
Output Status Signals
duration, refer to the
2–10:
duration, refer to the
rx_analogreset
rx_digitalreset
tx_digitalreset
rx_freqlocked
You can configure PCIe functional mode with or without the receiver clock rate
compensation FIFO in the Cyclone IV GX device. The reset sequence remains the
same whether or not you use the receiver clock rate compensation FIFO.
PCIe Reset Sequence
The PCIe protocol consists of an initialization/compliance phase and a normal
operation phase. The reset sequences for these two phases are described based on the
timing diagram in
pll_areset
pll_locked
busy (5)
Cyclone IV Device Datasheet
Cyclone IV Device Datasheet
1
Initialization / Compliance Phase
1 μs
Figure
2
Two parallel
clock cycles
2–10.
chapter.
(Note 1),(2)
chapter.
3
4
5
8
t
LTD_Auto
6
7
(4)
Chapter 2: Cyclone IV Reset Control and Power Down
9
Normal Operation Phase
Ignore receive data
10
© December 2010 Altera Corporation
t
LTD_Manual
11
(3)
Transceiver Reset Sequences
12
> two parallel
_
clock cycles
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