EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 299
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EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX150CF23I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
© December 2010 Altera Corporation
1
Figure 1–19. Receiver Polarity Inversion
The generic receiver polarity inversion feature is different from the PCI Express (PIPE)
8B/10B polarity inversion feature. The generic receiver polarity inversion feature
inverts the polarity of the data bits at the input of the word aligner and is not available
in PCI Express (PIPE) mode. The PCI Express (PIPE) 8B/10B polarity inversion
feature inverts the polarity of the data bits at the input of the 8B/10B decoder and is
available only in PCI Express (PIPE) mode.
The rx_invpolarity signal is dynamic and might cause initial disparity errors in
an 8B/10B encoded link. The downstream system must be able to tolerate these
disparity errors.
■
Receiver bit reversal—by default, the Cyclone IV GX receiver assumes LSB to MSB
transmission. If the link transmission order is MSB to LSB, the receiver forwards
the incorrect reverse bit-ordered version of the parallel data to the FPGA fabric on
the rx_dataout port. The receiver bit reversal feature is available to correct this
situation. This feature is static in manual alignment and automatic
synchronization state machine mode. In bit-slip mode, you can dynamically
enable the receiver bit reversal using the rx_revbitorderwa port. When
enabled, the 8-bit or 10-bit data D[7..0] or D[9..0] at the output of the word
aligner is rewired to D[0..7] or D[0..9] respectively.
receiver bit reversal feature.
Output from deserializer
0
1
1
1
0
0
0
1
0
0
MSB
LSB
rx_invpolarity = HIGH
Input to word aligner
1
0
0
0
1
1
1
0
1
1
Cyclone IV Device Handbook, Volume 2
MSB
LSB
Figure 1–20
shows the
1–19
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