EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 72
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EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX150CF23I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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5–10
Figure 5–1. Clock Control Block
Notes to
(1) The clkswitch signal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature. The
(2) The clkselect[1..0] signals are fed by internal logic and are used to dynamically select the clock source for the GCLK when the device is
(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not feasible.
(4) Two out of four PLL clock outputs are selected from adjacent PLLs to drive into the clock control block.
(5) You can use internal logic to enable or disable the GCLK in user mode.
(6) CLK[n] is not available on the left side of Cyclone IV E devices.
Cyclone IV Device Handbook, Volume 1
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n] (6)
output of the multiplexer is the input clock (f
in user mode.
Figure
Not applicable to
Cyclone IV E devices
f
5–1:
Figure 5–1
Each PLL generates five clock outputs through the c[4..0] counters. Two of these
clocks can drive the GCLK through a clock control block, as shown in
For more information about how to use the clock control block in the Quartus II
software, refer to the
inclk1
inclk0
inclk1
inclk0
Static Clock Select (3)
CLKSWITCH (1)
CLKSWITCH (1)
shows the clock control block.
f
f
IN
IN
IN
) for the PLL.
PLL
PLL
ALTCLKCTRL Megafunction User
C0
C1
C2
C3
C4
C0
C1
C2
C3
C4
Internal Logic
DPCLK
(4)
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
CLKSELECT[1..0] (2)
Clock Control Block
Guide.
Static Clock
© December 2010 Altera Corporation
Select (3)
Enable/
Disable
Internal Logic (5)
Figure
Clock Networks
5–1.
Global
Clock
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