EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 195
EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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3 000
Part Number:
EP4CGX150CF23I7N
Manufacturer:
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Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
Figure 8–11
interfaces to minimize signal integrity issues.
Figure 8–11. Balanced Star Routing
Notes to
(1) Altera recommends that M does not exceed 6 inches, as listed in
(2) Altera recommends using a balanced star routing. Keep the N length equal and as short as possible to minimize
Estimating AP Configuration Time
AP configuration time is dominated by the time it takes to transfer data from the
parallel flash to Cyclone IV E devices. This parallel interface is clocked by the
Cyclone IV E DCLK output (generated from an internal oscillator). The DCLK
minimum frequency when using the 40-MHz oscillator is 20 MHz (50 ns). In
word-wide cascade programming, the DATA[15..0] bus transfers a 16-bit word and
essentially cuts configuration time to approximately 1/16 of the AS configuration
time.
Equation 8–4.
Equation 8–5.
RBF Size
reflection noise from the transmission line. The M length is applicable for this setup.
Equation 8–4
Figure
maximum DCLK period
------------------------------------------------------ -
16 bits per DCLK cycle
shows the recommended balanced star routing for multiple bus master
8–11:
and
Master Device
Cyclone IV E
Equation 8–5
DCLK
9,600,000 bits
=
estimated maximum configuration time
show the configuration time calculations.
M (1)
50 ns
------------ -
16 bit
=
Table 8–9 on page
30 ms
Numonyx Flash
Master Device
External
Cyclone IV Device Handbook, Volume 1
N (2)
N (2)
8–27.
8–29
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