EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 85
EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX150CF23I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Feedback Modes
No Compensation Mode
© December 2010 Altera Corporation
In no compensation mode, the PLL does not compensate for any clock networks. This
provides better jitter performance because clock feedback into the PFD does not pass
through as much circuitry. Both the PLL internal and external clock outputs are phase
shifted with respect to the PLL clock input.
Figure 5–13
this mode.
Figure 5–13. Phase Relationship Between PLL Clocks in No Compensation Mode
Notes to
(1) Internal clocks fed by the PLL are phase
(2) The PLL clock outputs can lead or lag the PLL input clocks.
Figure
shows a waveform example of the phase relationship of the PLL clock in
5–13:
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
(1), (2)
External PLL Clock
Outputs
(2)
Phase Aligned
-
aligned to each other.
Cyclone IV Device Handbook, Volume 1
5–23
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