EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 151

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
SSTL-3 Class II
AGP (1 and 2 )
CTT
Table 2–32. I/O Support by Bank (Part 2 of 2)
I/O Standard
Each I/O bank has its own VCCIO pins. A single device can support 1.5-,
1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different standard
independently. Each bank also has dedicated VREF pins to support any
one of the voltage-referenced standards (such as SSTL-3) independently.
Each I/O bank can support multiple standards with the same V
input and output pins. Each bank can support one voltage-referenced
I/O standard. For example, when V
LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
Differential On-Chip Termination
Stratix devices provide differential on-chip termination (LVDS I/O
standard) to reduce reflections and maintain signal integrity. Differential
on-chip termination simplifies board design by minimizing the number
of external termination resistors required. Termination can be placed
inside the package, eliminating small stubs that can still lead to
reflections. The internal termination is designed using transistors in the
linear region of operation.
Stratix devices support internal differential termination with a nominal
resistance value of 137.5
signals require an external termination resistor.
device with differential termination.
Top & Bottom Banks
(3, 4, 7 & 8)
v
v
v
for LVDS input receiver buffers. LVPECL
Left & Right Banks
(1, 2, 5 & 6)
v
v
CCIO
Stratix Device Handbook, Volume 1
is 3.3 V, a bank can support
Figure 2–71
Enhanced PLL External
Clock Output Banks
(9, 10, 11 & 12)
Stratix Architecture
v
v
v
shows the
CCIO
2–127
for