EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 352

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Clocking
1–42
Stratix Device Handbook, Volume 2
CLK0p/n
CLK1p/n
CLK2p/n
CLK3p/n
CLK4p/n
CLK5p/n
CLK6p/n
CLK7p/n
CLK8p/n
CLK9p/n
CLK10p/n
CLK11p/n
CLK12p/n
CLK13p/n
CLK14p/n
CLK15p/n
Table 1–14. Stratix Clock Input Sources For Enhanced & Fast PLLs (Part 1 of 2)
Clock Input
Pins
PLL 1
(1)
v
v
PLL 2
(1)
v
v
Input clocks for fast PLLs 1, 2, 3, and 4 come from CLK pins. Stratix GX
devices use PLLs 3 and 4 in the HSSI block only. A multiplexer chooses
one of two possible CLK pins to drive each PLL. This multiplexer is not a
clock switchover multiplexer and is only used for clock input
connectivity.
Either a FPLLCLK input pin or a CLK pin can drive the fast PLLs in the
corners (7, 8, 9, and 10) when used for general purpose. CLK pins cannot
drive these fast PLLs in high-speed differential I/O mode. PLLs 9 and 10
are used for the HSSI block in Stratix GX devices and are not available.
Table 1–14
which input clock pin drives which PLLs.
All Stratix Devices
PLL 3
(1)
v
v
PLL 4
shows which PLLs are available for each Stratix device and
(1)
v
v
PLL 5
(2)
v
v
PLL 6
(2)
v
v
PLL 7
EP1S30, EP1S40, EP1S60 &
(1)
v
EP1S80 Devices Only
PLL 8
(1)
v
PLL 9
(1)
v
10
PLL
v
Altera Corporation
(1)
11
Devices Only
EP1S40 (3),
PLL
v
v
EP1S60 &
EP1S80
(2)
July 2005
12
PLL
v
v
(2)