EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 768

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Configuration Schemes
11–50
Stratix Device Handbook, Volume 2
Example Jam File that Reads the IDCODE
Figure 11–27
example reads the IDCODE out of a single device in a JTAG chain.
1
Figure 11–27. Example Jam File Reading IDCODE
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
BOOLEAN read_data[32];
BOOLEAN I_IDCODE[10] = BIN 1001101000; ‘assumed
BOOLEAN ONES_DATA[32] = HEX FFFFFFFF;
INTEGER i;
‘Set up stop state for IRSCAN
IRSTOP IRPAUSE;
‘Initialize device
STATE RESET;
IRSCAN 10, I_IDCODE[0..9]; ‘LOAD IDCODE INSTRUCTION
STATE IDLE;
WAIT 5 USEC, 3 CYCLES;
DRSCAN 32, ONES_DATA[0..31], CAPTURE
read_data[0..31];
‘CAPTURE IDCODE
PRINT “IDCODE:”;
FOR i=0 to 31;
PRINT read_data[i];
NEXT i;
EXIT 0;
Table 11–14. Reserved Keywords (Part 2 of 2)
IEEE Std. 1149.1 JTAG State Names
The array variable, I_IDCODE, is initialized with the IDCODE
instruction bits ordered the LSB first (on the left) to most
significant bit (MSB) (on the right). This order is important
because the array field in the IRSCAN instruction is always
interpreted, and sent, MSB to LSB.
illustrates the flexibility and utility of the Jam STAPL. The
IRCAPTURE
IRSHIFT
IREXIT1
IRPAUSE
IREXIT2
IRUPDATE
Jam Reserved State Names
Altera Corporation
July 2005