EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 705

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
Notes to
(1)
(2)
(3)
(4)
Programmable duty cycle
PLL clock outputs can feed
logic array
PLL locked output can feed
the logic array
Multiplication allowed in
zero-delay buffer mode or
external feedback mode
Programmable phase shift
allowed in zero-delay buffer
mode or external feedback
mode
Phase frequency detector
(PFD) disable
Clock output disable
Programmable lock detect &
gated lock
Dynamic clock switchover
PLL reconfiguration
Programmable bandwidth
Spread spectrum
Table 10–7. Stratix & Stratix GX Enhanced PLL Features
These features are also available in fast PLLs.
In addition to the delay chains at each counter, you can specify the programmable phase shift for each PLL output
at fine and coarse levels.
Each PLL clock output has an associated clock enable signal.
If the PLL is used in external feedback mode, the PLL will need to relock.
(2)
Table
Feature
(1)
(1)
10–7:
(3)
(1)
advanced features to improve system timing management and
performance.
Stratix and Stratix GX enhanced PLLs.
Fast PLLs
Stratix and Stratix GX fast PLLs are similar to the APEX II True-LVDS
PLLs in that the W setting, which governs the relationship between the
clock input and the data rate, and the J setting, which controls the width
Allows the counters and delay elements within the PLL to be reconfigured in real-
Provides advanced control of the PLL bandwidth by using the programmable
Modulates the target frequency over a frequency range to reduce
Allows variable duty cycle for each PLL clock output.
Allows the PLL clock outputs to feed data ports of registers or combinatorial logic.
Allows the PLL locked port to feed data ports of registers or combinatorial logic.
The PLL clock outputs can be a multiplied or divided down ratio of the PLL input
clock.
The PLL clock outputs can be phase shifted. The phase shift is relative to the PLL
clock output.
Allows the VCO to operate at its last set control voltage and frequency with some
long term drift.
PLL maintains lock with output clocks disabled.
Holds the lock signal low for a programmable number of input clock cycles.
Enables the PLL to switch between two reference input clocks, either for clock
redundancy or dual-clock domain applications.
time without reloading a programmer object file (.pof).
control of the PLL loop characteristics.
electromagnetic interference (EMI) emissions.
Table 10–7
Transitioning APEX Designs to Stratix & Stratix GX Devices
shows some of the new features available in
Description
Stratix Device Handbook, Volume 2
(4)
10–21