EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 391

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 2–13. Single-Port Mode
Notes to
(1)
(2)
(3)
Designing With
TriMatrix
Memory
Altera Corporation
July 2005
address[ ]
outclken
outclock
inclken
inclock
data[ ]
wren
For more information on the MultiTrack interconnect, see the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Figure
8 LAB Row
Clocks
8
2–13:
Single-Port Mode
The TriMatrix memory blocks can implement single-port clock mode for
single-port memory mode. Single-port mode is used when simultaneous
reads and writes are not required. See
memory block can support up to two single-port mode RAM blocks in
M4K blocks.
When instantiating TriMatrix memory you must understand the various
features that set it apart from other memory architectures. The following
sections describe some of the important attributes and functionality of
TriMatrix memory.
Notes
D
ENA
D
ENA
(1), (2),
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Q
Q
(3)
Generator
D
ENA
Pulse
Write
Q
Data In
Address
Write Enable
RAM/ROM
1,024 × 4
2,048 × 2
4,096 × 1
Data Out
256 × 16
512 × 8
Figure
Stratix Device Handbook, Volume 2
2–13. A single block in a
D
ENA
Q
To MultiTrack
Interconnect
2–23