MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 168

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
the bus cycle to the processor through the use of the DSACKx inputs. Refer
to Table 7-1 for DSACKx encodings and assertion results.
word operand from a long-word aligned address, it attempts to read 32 bits
of a word or byte address.) If the port responds that it is 32 bits wide, the
the port responds that it is 16 bits wide, the MC68030 latches the 16 bits of
valid data and runs another bus cycle to obtain the other 16 bits. The operation
for an 8-bit port is similar, but requires four read cycles. The addressed device
device
to or from a particular port size be fixed. A 32-bit port must reside on data
The bytes of operands are designated as shown in Figure 7-3. The most
signals its port size (byte, word, or long word) and indicates completion of
For example, if the processor is executing an instruction that reads a long-
during the first bus cycle. (Refer to 7.2.2 Misaligned Operands for the case
MC68030 latches all 32 bits of data and continues with the next operation. If
uses the DSACKx signals to indicate the port width. For instance, a 32-bit
bus cycle is a byte, word, or long-word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer
bus bits 0-31, a 16-bit port must reside on
port must reside on data bus bits 24-31. This requirement minimizes the
number of bus cycles needed to transfer data to 8- and 16-bit ports and
ensures that the MC68030 correctly transfers valid data. The MC68030 always
attempts to transfer the maximum amount of data on all bus cycles; for a
beginning the bus cycle.
significant byte of a long-word operand is OP0, and OP3 is the least significant
byte. The two bytes of a word-length operand are OP2 (most significant) and
OP3. The single byte of a byte-length operand is OP3. These designations
are used in the figures and descriptions that follow.
long-word operation, it always assumes that the port is 32 bit wide when
a/ways
DSACK1
H
H
L
returns DSACKx for a 32-bit port (regardless of whether the
Table 7-1. DSACK Codes and Results
DSACK0
MC68030 USER'S MANUAL
H
H
L
Inse.~ Wait States in Current Bus Cycle
Complete Cycle-- Data Bus PortSize is 16 Bits
Complete Cycle -- Data Bus Port Size is 32 Bits
Complete Cycle -- Data Bus Port Size is 8 Bits
data
Result
bus bits 16-32, and an 8-bit
7-7
El