MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 230

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.4.1 Interrupt Acknowledge Bus Cycles
MOTOROLA
A C K N O W L E D G E
A C K N O W L E D G E
COPROCESSOR
B R E A K P O I N T
I N T E R R U P T
COMM.
three of the encodings are implemented as shown in Figure 7-42. All unused
values are reserved by Motorola for future additional CPU space types.
that the device requires serv ce, and the internally synchronized value on
The CPU space type s encoded on A16-A19 during a CPU space operation
and indicates the function that the processor is performing. On the MC68030,
When a peripheral device signals the processor (with the IPL0-1PL2 signals)
these signals indicates a higher priority than the interrupt mask in the status
the processor makes the interrupt a pending interrupt. Refer to 8.1.9 Interrupt
The MC68030 takes an interrupt exception for a pending interrupt within one
terrupt acknowledge bus cycles that can be executed as part of interrupt
register (or that a transition has occurred in the case of a level 7 interrupt),
Exceptions for details on the recognition of interrupts.
instruction boundary (after processing any other pending exception with a
higher priority). The following paragraphs describe the various kinds of in-
exception processing.
F U N C T I O N
2
2
2
C O D E
0
O
0
Figure 7-42. NIC68030 CPU Space Address Encoding
I o O OC o o
JO O 0 0 0 O 0 0 O 0 0 0
["
,,
31
31
1
1
1
MC68030 USER'S MANUAL
•
o 0 o o o OlO 0 0 OlO 0 0 0 0 0 0 0 0 0
1
i
123
1
1
i
1]1
,
I
ADDRESS BUS
,0
i
CPU SPACE
TYPE FIELD
~
1
1
l
1 111
0
,,
15
I
I
1
13
1
,
0 0 0 0 0 O O L
1
1
I
1
01 B'P" fD 01
1
1
,
4
3
1
~
CPREG l
,
1
7-69
1 0
0
O
7